ASX340CS datasheet(36/74 Pages) ONSEMI

36 / 74 page

ASX340CS_DS Rev. F Pub. 6/15 EN

©Semiconductor Components Industries, LLC, 2015.

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Slave Two-Wire Serial Interface

The two-wire serial interface bus enables read/write access to control and status regis-

ters within the ASX340CS. This interface is designed to be compatible with the MIPI Alli-

ance Standard for Camera Serial Interface 2 (CSI-2) 1.0, which uses the electrical

characteristics and transfer protocols of the two-wire serial interface specification.

The interface protocol uses a master/slave model in which a master controls one or

more slave devices. The sensor acts as a slave device. The master generates a clock

(SCLK) that is an input to the sensor and used to synchronize transfers.

Data is transferred between the master and the slave on a bidirectional signal (SDATA).

SDATA is pulled up to VDD_IO off-chip by a pull-up resistor in the range of 1.5 to 4.7k

resistor.

Protocol

Data transfers on the two-wire serial interface bus are performed by a sequence of low-

level protocol elements, as follows:

• a start or restart condition

• a slave address/data direction byte

• a 16-bit register address

• an acknowledge or a no-acknowledge bit

•data bytes

• a stop condition

The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with

a start condition, and the bus is released with a stop condition. Only the master can gen-

erate the start and stop conditions.

The SADDR pin is used to select between two different addresses in case of conflict with

another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave

address is 0xBA. See Table 19.

Start Condition

A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.

At the end of a transfer, the master can generate a start condition without previously

generating a stop condition; this is known as a “repeated start” or “restart” condition.

Data Transfer

Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of

data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte and for message bytes.

One data bit is transferred during each SCLK clock period. SDATA can change when SCLK

is low and must be stable while SCLK is HIGH.

Table 19:

Two-Wire Interface ID Address Switching

SADDR

Two-Wire Interface Address ID

00x90

10xBA

ASX340CS 数据表(PDF) 36 Page - ON Semiconductor

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