ASX340CS datasheet(38/74 Pages) ONSEMI

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ASX340CS_DS Rev. F Pub. 6/15 EN

©Semiconductor Components Industries, LLC, 2015.

ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Slave Two-Wire Serial Interface

Typical Operation

A typical READ or WRITE sequence begins by the master generating a start condition on

the bus. After the start condition, the master sends the 8-bit slave address/data direction

byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”

indicates a WRITE and a “1” indicates a READ. If the address matches the address of the

slave device, the slave device acknowledges receipt of the address by generating an

acknowledge bit on the bus.

If the request was a WRITE, the master then transfers the 16-bit register address to which

a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave

sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master will then transfer the 16-bit data, as two 8-bit sequences and the

slave sends an acknowledge bit after each sequence to indicate that the byte has been

received. The master stops writing by generating a (re)start or stop condition. If the

request was a READ, the master sends the 8-bit write slave address/data direction byte

and 16-bit register address, just as in the write request. The master then generates a

(re)start condition and the 8-bit read slave address/data direction byte, and clocks out

the register data, 8 bits at a time. The master generates an acknowledge bit after each

8-bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.

Single READ from Random Location

Figure 17 shows the typical READ cycle of the host to the ASX340CS. The first two bytes

sent by the host are an internal 16-bit register address. The following 2-byte READ cycle

sends the contents of the registers to host.

Figure 17:

Single READ from Random Location

Single READ from Current Location

Figure 18 shows the single READ cycle without writing the address. The internal address

will use the previous address value written to the register.

Figure 18:

Single Read from Current Location

S = start condition

P = stop condition

Sr = restart condition

A = acknowledge

A = no-acknowledge

slave to master

master toslave

Slave Address

A Reg Address[15:8]

Reg Address[7:0]

Slave Address

Read Data

[15:8]

Previous RegAddress, N

Reg Address, M

M+1

Read Data

[7:0]

Slave Address

Read Data

[15:8]

Slave Address

Read Data

[15:8]

Previous Reg Address, N

Reg Address, N+1

N+2

Read Data

[7:0]

Read Data

[7:0]

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