TSC2000IPW datasheet(13/34 Pages) TI

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TSC2000

SBAS257

ADDR

Reserved

BAT1

BAT2

AUX1

AUX2

TEMP1

TEMP2

DAC

Reserved

ZERO

Reserved

PAGE 0: DATA REGISTERS

PAGE 1: CONTROL REGISTERS

ADDR

ADC

Reserved

DACCTL

REF

RESET

CONFIG

Reserved

TABLE III. TSC2000 Memory Map.

FIGURE 7. Write and Read Operation of TSC2000 Interface.

Write Operation

Read Operation

Command Word

Data

SCLK

MOSI

MISO

To read all the first page of memory, for example, the host

processor must send the TSC2000 the command 8000H—this

specifies a read operation beginning at Page 0, Address 0. The

processor can then start clocking data out of the TSC2000. The

TSC2000 will automatically increment its address pointer to the

end of the page; if the host processor continues clocking data

out past the end of a page, the TSC2000 will simply send back

the value FFFFH.

Likewise, writing to Page 1 of memory would consist of the

processor writing the command 0800H, which would specify a

write operation, with PG0 set to 1, and all the ADDR bits set

to 0. This would result in the address pointer pointing at the

first location in memory on Page 1. See the TSC2000 Memory

Map section for details of register locations. Figure 7 shows an

example of a complete data transaction between the host

processor and the TSC2000.

TSC2000 MEMORY MAP

The TSC2000 has several 16-bit registers which allow control

of the device as well as providing a location for results from the

TSC2000 to be stored until read by the host microprocessor.

These registers are separated into two pages of memory in the

TSC2000: a Data page (Page 0) and a Control page (Page 1).

The memory map is shown in Table III.

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