TSC2000IPW datasheet(33/34 Pages) TI

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TSC2000

SBAS257

FIGURE 29. D/A Converter Circuit when Using V+ Higher

than VSUPPLY.

D/A Converter

V+

SUPPLY

BIAS

OUT

ARNG

RRNG

8 Bits

In the previous example, when the D/A converter current is

zero, the voltage on the AOUT pin will rise above the TSC2000

supply voltage. This is not a problem, however, since V+ was

within the absolute maximum ratings of the TSC2000, so no

special precautions are necessary. Many LCD displays re-

quire voltages much higher than the absolute maximum

ratings of the TSC2000. In this case, the addition of an NPN

transistor, as shown in Figure 29, will protect the AOUT pin

from damage.

result. Such glitches might originate from switching power

supplies, nearby digital logic, and high power devices. The

degree of error in the digital output depends on the reference

voltage, layout, and the exact timing of the external event.

The error can change if the external event changes in time

with respect to the SCL input.

With this in mind, power to the TSC2000 should be clean and

well bypassed. A 0.1

µF ceramic bypass capacitor should be

placed as close to the device as possible. A 1

µF to 10µF

capacitor may also be needed if the impedance of the

connection between +VDD and the power supply is HIGH.

A bypass capacitor is generally not needed on the reference

pin because the reference is buffered by an internal op amp.

If an external reference voltage originates from an op amp,

make sure that it can drive any bypass capacitor that is used

without oscillation.

The TSC2000 architecture offers no inherent rejection of

noise or voltage variation in regards to using an external

reference input. This is of particular concern when the

reference input is tied to the power supply. Any noise and

ripple from the supply will appear directly in the digital results.

While high frequency noise can be filtered out, voltage

variation due to line frequency (50Hz or 60Hz) can be difficult

to remove.

The GND pin should be connected to a clean ground point.

In many cases, this will be the “analog” ground. Avoid

connections which are too near the grounding point of a

microcontroller or digital signal processor. If needed, run a

ground trace directly from the converter to the power supply

entry or battery connection point. The ideal layout will include

an analog ground plane dedicated to the converter and

associated analog circuitry.

In the specific case of use with a resistive touch screen, care

should be taken with the connection between the converter

and the touch screen. Since resistive touch screens have

fairly low resistance, the interconnection should be as short

and robust as possible. Loose connections can be a source

of error when the contact resistance changes with flexing or

vibrations.

As indicated previously, noise can be a major source of error

in touch screen applications (e.g., applications that require a

back-lit LCD panel). This EMI noise can be coupled through

the LCD panel to the touch screen and cause “flickering” of

the converted data. Several things can be done to reduce

this error, such as utilizing a touch screen with a bottom-side

metal layer connected to ground. This will couple the majority

of noise to ground. Additionally, filtering capacitors, from Y+,

Y–, X+, and X– to ground, can also help. Note, however, that

the use of these capacitors will increase screen settling time

and require longer panel voltage stabilization times, as well

as increased precharge and sense times for the PENIRQ

circuitry of the TSC2000.

LAYOUT

The following layout suggestions should provide optimum

performance from the TSC2000. However, many portable

applications have conflicting requirements concerning power,

cost, size, and weight. In general, most portable devices

have fairly “clean” power and grounds because most of the

internal components are very low power. This situation would

mean less bypassing for the converter’s power and less

concern regarding grounding. Still, each situation is unique

and the following suggestions should be reviewed carefully.

For optimum performance, care should be taken with the

physical layout of the TSC2000 circuitry. The basic SAR

architecture is sensitive to glitches or sudden changes on the

power supply, reference, ground connections, and digital

inputs that occur just prior to latching the output of the analog

comparator. Therefore, during any single conversion for an

‘n-bit’ SAR converter, there are n ‘windows’ in which large

external transient voltages can easily affect the conversion

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