TSC2000IPW datasheet(16/34 Pages) TI

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TSC2000

SBAS257

AV1

AV0

FUNCTION

None

4 Data Averages

8 Data Averages

16 Data Averages

TABLE X. A/D Conversion Averaging Control.

CL1

CL0

FUNCTION

8MHz Internal Clock Rate—8-Bit Resolution Only

4MHz Internal Clock Rate—10-Bit Resolution Only

2MHz Internal Clock Rate.

1MHz Internal Clock Rate.

TABLE XI. A/D Converter Clock Control.

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DPD

TABLE XIII. D/A Converter Control Register.

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

INT

DL1

DL0

PDN

RFV

TABLE XV. Reference Register.

PV2

PV1

PV0

FUNCTION

µs Stabilization Time

100

µs Stabilization Time

500

µs Stabilization Time

1ms Stabilization Time

5ms Stabilization Time

10ms Stabilization Time

50ms Stabilization Time

100ms Stabilization Time

TABLE XII. Panel Voltage Stabilization Time Control.

DPD

VALUE

DESCRIPTION

D/A Converter is Powered and Operational

D/A Converter is Powered Down

TABLE XIV. DPD Bit Operation.

INT

VALUE

DESCRIPTION

External Reference Selected

Internal Reference Selected

TABLE XVI. INT Bit Operation.

Bits[7:6]: AV1, AV0 = Converter Averaging Control. These

two bits allow you to specify the number of averages the

converter will perform, as shown in Table X. Note that when

averaging is used, the STS bit and the DAV output will

indicate that the converter is busy until all conversions

necessary for the averaging are complete. The default state

for these bits is 00, selecting no averaging. These bits are the

same whether reading or writing.

Bits[5:4]: CL1, CL0 = Conversion Clock Control. These two

bits specify the internal clock rate which the A/D converter uses

when performing a single conversion, as shown in Table XI.

These bits are the same whether reading or writing.

Bits [3:1]: PV2 – PV0 = Panel Voltage Stabilization Time

control. These bits allow you to specify a delay time from the

time a pen touch is detected to the time a conversion is

started. This allows you to select the appropriate settling time

for the touch panel used. Table XII shows the settings of

these bits. The default state is 000, indicating a 0ms stabili-

zation time. These bits are the same whether reading or

writing.

Bit 0: This bit is not used, and is a “don’t care” when writing.

It will always read as a zero.

D/A CONVERTER CONTROL REGISTER

(PAGE 1, ADDRESS 02H)

The single bit in this register controls the power down control

of the on-board D/A converter. This register is formatted as

shown in Table XIII.

Bit 15: DPD = D/A Converter Power Down. This bit controls

whether the D/A converter is powered up and operational, or

powered down. If the D/A converter is powered down, the

AOUT pin will neither sink nor source current.

REFERENCE REGISTER

(PAGE 1, ADDRESS 03H)

The TSC2000 has a register to control the operation of the

internal reference. This register is formatted as shown in

Table XV.

Bit 4: INT = Internal Reference Mode. If this bit is written to

a 1, the TSC2000 will use its internal reference; if this bit is

a zero, the part will assume an external reference is being

supplied. The default state for this bit is to select an external

reference (0). This bit is the same whether reading or writing.

Bits [3:2]: DL1, DL0 = Reference Power-Up Delay. When

the internal reference is powered up, a finite amount of time

is required for the reference to settle. If measurements are

made before the reference has settled, these measurements

will be in error. These bits allow for a delay time for measure-

ments to be made after the reference powers up, thereby

assuring that the reference has settled. Longer delays will be

necessary depending upon the capacitance present at the

REF pin (see Typical Characteristics).

See Table XVII for the delays. The default state for these bits

is 00, selecting a 0ms delay. These bits are the same

whether reading or writing.

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