数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

ADE3100 数据表(PDF) 17 Page - STMicroelectronics

部件名 ADE3100
功能描述  LCD Display Engines with Integrated DVI, ADC and YUV Ports
PDF  88 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3100 数据表(HTML) 17 Page - STMicroelectronics

Back Button ADE3100 Datasheet HTML 13Page - STMicroelectronics ADE3100 Datasheet HTML 14Page - STMicroelectronics ADE3100 Datasheet HTML 15Page - STMicroelectronics ADE3100 Datasheet HTML 16Page - STMicroelectronics ADE3100 Datasheet HTML 17Page - STMicroelectronics ADE3100 Datasheet HTML 18Page - STMicroelectronics ADE3100 Datasheet HTML 19Page - STMicroelectronics ADE3100 Datasheet HTML 20Page - STMicroelectronics ADE3100 Datasheet HTML 21Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 17 / 88 page
background image
17/88
ADE3XXX
FM Frequency Synthesizer
2.2
FM Frequency Synthesizer
The FM frequency synthesizer creates a clock equivalent to up to eight times the crystal input clock,
using a digital frequency synthesizer. The modulation period and amplitude are directly controlled
by I2C registers. The I2C interface runs in the LLK_CTRL clock domain, which must be active for
access.
The output frequency (fOUT) is related to the 32-bit PHASE_RATE and crystal frequency (fXCLK) as
follows:
fOUT = fXCLK x 2
27+NDIV / PHASE_RATE
GLBL_CLK_SRC_SEL_3
0x0012
[7]
Reserved
R/W
[6:4]
0x4
YUV clock source
0x0: YUVCLK pin
0x1: SCLK freq synth
0x2: YUVCLK pin (normal)
0x3: CLKIN pin
0x4: crystal clock
0x5: 0
0x6 - 0x7: Reserved
[3]
Reserved
R/W
[2:0]
0x4
DVI detection clock source
0x0: YUVCLK pin
0x1: SCLK freq synth
0x2: DVI detect clock (normal)
0x3: CLKIN pin
0x4: crystal clock
0x5: 0
0x6 - 0x7: Reserved
GLBL_IK_SRST
0x0020
R/W
[7]
0x0
HDCP block reset synchronous to INCLK
R/W
[6]
0x0
DFT block reset synchronous to INCLK
R/W
[5]
0x0
ADC block reset synchronous to INCLK
R/W
[4]
0x0
SCALER block reset synchronous to INCLK
R/W
[3]
0x0
YUV block reset synchronous to INCLK
R/W
[2]
0x0
DVI block reset synchronous to INCLK
R/W
[1]
0x0
DMEAS block reset synchronous to INCLK
R/W
[0]
0x0
SMUX block reset synchronous to INCLK
GLBL_DK_SRST
0x0040
[7]
0x0
Reserved
R/W
[6]
0x0
PGEN block reset synchronous to DOTCLK
R/W
[5]
0x0
OMUX block reset synchronous to DOTCLK
R/W
[4]
0x0
APC block reset synchronous to DOTCLK
R/W
[3]
0x0
OSD block reset synchronous to DOTCLK
R/W
[2]
0x0
GAMMA block reset synchronous to
DOTCLK
R/W
[1]
0x0
OSQ block reset synchronous to DOTCLK
R/W
[0]
0x0
SCALE block reset synchronous to DOTCLK
Table 4: Global Registers (Sheet 4 of 4)
Register Name
Addr.
Mode
Bits
Default
Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com