ADE3100 datasheet(20/88 Pages) STMICROELECTRONICS

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Line Lock PLL Block

ADE3XXX

20/88

LLK_PLL_CTRL

0x0801

R/W

[7:6]

Reserved

R/W

[5]

0x0

0: normal

1: diagnostic mode -- PLL uses only fine

error

R/W

[4]

0x0

0: normal

1: diagnostic -- coarse error is multiplied by

R/W

[3]

0x0

input hsync edge selection

0: rising edge

1: falling edge

R/W

[2]

0x0

sync on green input selection

0: composite sync (HSYNC pin)

1: sync on green (CSYNC pin)

R/W

[1]

0x0

0: normal

1: divide PLL clock by 2

R/W

[0]

0x0

0: normal

1: Free-running mode

LLK_PLL_MFACTOR_L

0x0802

R/W

[7:0]

0x0280

number of clocks in a line

LLK_PLL_MFACTOR_H

0x0803

R/W

[7:0]

LLK_PLL_HPERIOD_L

0x0804

R/W

[7:0]

0x0040

pulse width of synthetic hsync

LLK_PLL_HPERIOD_H

0x0805

R/W

[7:0]

LLK_PLL_PHASE_RATE_INIT_0

0x0806

R/W

[7:0]

0x0

Initial Phase Rate

LLK_PLL_PHASE_RATE_INIT_1

0x0807

R/W

[7:0]

fOUT = fXTAL x 2

27+NDIV / PHASE_RATE

LLK_PLL_PHASE_RATE_INIT_2

0x0808

R/W

[7:0]

LLK_PLL_PHASE_RATE_INIT_3

0x0809

R/W

[7:0]

LLK_PLL_PHASE_RATE_INIT_WR

0x080A

R/W

[7:1]

Reserved

[0]

When written to 1, the PLL phase rate is

initialized with the initial phase rate register.

Self clearing.

LLK_PLL_TC_AEF

0x080B

[7:4]

Reserved

R/W

[3:0]

0xA

Fast Time Constant A Exponent

LLK_PLL_TC_BEF

0x080C

[7:4]

Reserved

R/W

[3:0]

0xA

Fast Time Constant B Exponent

LLK_PLL_TC_ALF

0x080D

[7:6]

Reserved

R/W

[5:0]

0x20

Fast Time Constant A Linear

LLK_PLL_TC_BLF

0x080E

[7:6]

Reserved

R/W

[5:0]

0x20

Fast Time Constant B Linear

LLK_PLL_TC_AES

0x080F

[7:4]

Reserved

R/W

[3:0]

0x6

Slow Time Constant A Exponent

LLK_PLL_TC_BES

0x0810

[7:4]

Reserved

R/W

[3:0]

0x6

Slow Time Constant B Exponent

LLK_PLL_TC_ALS

0x0811

[7:6]

Reserved

R/W

[5:0]

0x20

Slow Time Constant A Linear

Table 7: Line Lock PLL Registers (Sheet 2 of 4)

Addr

Mode

Bits

Default

Description

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ADE3100 数据表(PDF) 20 Page - STMicroelectronics

ADE3100 数据表(HTML) 20 Page - STMicroelectronics

Html Pages

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