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ADE3100 数据表(PDF) 53 Page - STMicroelectronics |
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ADE3100 数据表(HTML) 53 Page - STMicroelectronics |
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53 / 88 page ![]() 53/88 ADE3XXX Output Sequencer Block Table 19: Output Sequencer Registers (Sheet 1 of 2) Register Name Addr Mode Bits Default Description OSQ_CONTROL 0x0BC1 R [7] out_vmax detected, sticky bit R/W [6] 0x0 out_vmax detect reset R/W [5] 0x0 interlace enable R/W [4] 0x0 fractional line extend 0: +1 1: +2 R/W [3] 0x0 frame lock reference 0: last input pixel 1: first input pixel R/W [2] 0x0 frame lock selection 0: last line variable 1: fixed line length R [1] shutdown ready - current frame has completed, panel can now be shut down R/W [0] 0x0 run sequencer when 1, otherwise stop at the end of the frame and set shutdown ready flag (bit [1]) OSQ_CLOCK_FRAC 0x0BC2 R/W [7:0] 0x0 the fraction of lines (/256) that are extended OSQ_OUT_HTOTAL_L 0x0BC3 R/W [7:0] 0x0 nominal output horizontal total [7:0] OSQ_OUT_HTOTAL_H 0x0BC4 [7:4] Reserved R/W [3:0] 0x0 nominal output horizontal total [11:8] OSQ_OUT_VTOTAL_MIN_L 0x0BC5 R/W [7:0] 0x0 minimum output vertical total, used to rearm for vert_enab trigger [7:0] OSQ_OUT_VTOTAL_MIN_H 0x0BC6 [7:4] Reserved R/W [3:0] 0x0 minimum output vertical total, used to rearm for vert_enab triggers [11:8] OSQ_VTOTAL_MAX_L 0x0BC7 R/W [7:0] 0x0 maximum output vertical total, prevents panel burn with loss of vert_enab trigger [7:0] OSQ_VTOTAL_MAX_H 0x0BC8 [7:4] Reserved R/W [3:0] 0x0 maximum output vertical total, prevents panel burn with loss of vert_enab triggers [11:8] OSQ_VERTEN_DLY_E_L 0x0BC9 R/W [7:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, even and non- interlaced modes [15:0] OSQ_VERTEN_DLY_E_M 0x0BCA R/W [7:0] 0x0 OSQ_VERTEN_DLY_E_H 0x0BCB [7:4] Reserved R/W [3:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, even and non- interlaced [19:16] OSQ_VERTEN_DLY_O_L 0x0BCC R/W [7:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, odd frame in interlace mode only [15:0] OSQ_VERTEN_DLY_O_M 0x0BCD R/W [7:0] 0x0 |
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