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ADE3000T 数据表(PDF) 21 Page - STMicroelectronics |
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ADE3000T 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 88 page  21/88 ADE3XXX Line Lock PLL Block LLK_PLL_TC_BLS 0x0812 [7:6] Reserved R/W [5:0] 0x20 Slow Time Constant B Linear LLK_PLL_TC_AEK 0x0813 [7:4] Reserved R/W [3:0] 0x6 Lock Time Constant A Exponent LLK_PLL_TC_BEK 0x0814 [7:4] Reserved R/W [3:0] 0x6 Lock Time Constant B Exponent LLK_PLL_TC_ALK 0x0815 [7:6] Reserved R/W [5:0] 0x20 Lock Time Constant A Linear LLK_PLL_TC_BLK 0x0816 [7:6] Reserved R/W [5:0] 0x20 Lock Time Constant B Linear LLK_PLL_TC_SLOW_TOL 0x0817 R/W [7:0] 0x80 More than SLOW_LINE_NB lines with a phase error less than the SLOW_TOL will set the slow status bit, and the PLL will work with the slow time constant. One or more lines with a phase error more than SLOW_TOL will reset the slow status bit, and the PLL will work with the fast time constant. LSB of SLOW_TOL is approx. 200ps. LLK_PLL_TC_SLOW_LINE_NB 0x0818 R/W [7:0] 0x10 LLK_PLL_LOCK_TOL 0x0819 R/W [7:0] 0x20 More than LOCK_LINE_NB lines with a phase error less than the LOCK_TOL will set the lock status bit, and the PLL will work with the lock time constant. One or more lines with a phase error more than LOCK_TOL will reset the lock status bit, and the PLL will work with the slow time constant. LSB of LOCK_TOL is approx. 200 ps. LLK_PLL_LOCK_LINE_NB 0x081A R/W [7:0] 0x30 LLK_PLL_PH_OFFSET 0x081B R/W [7:0] 0x0 Phase Adjustment. The maximum phase offset value is equal to PHASE_RATE[31:21] or 0x40, whichever is higher. LLK_PLL_PH_OFFSET_EN 0x081C R/W [7] 0x0 Phase Enable [6:0] Reserved LLK_PLL_PULSE_HIGH_EXT 0x081D R/W [7] 0x0 0: no pulse extend 1: extend pulse (normal) [6:3] Reserved R/W [2:0] 0x0 Pulse Extend Amount 0x0: Minimum 0x7: Maximum (Normal) LLK_PLL_STAT_LINES_L 0x081E R/W [7:0] 0x10 Number of lines to statistically analyze. LLK_PLL_STAT_LINES_H 0x081F R/W [7:0] LLK_PLL_STAT_ERROR_INC_LOW 0x0820 [7:0] Reserved Table 7: Line Lock PLL Registers (Sheet 3 of 4) Register Name Addr Mode Bits Default Description |
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