ADE3000T datasheet(29/88 Pages) STMICROELECTRONICS

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ADE3XXX

YUV Block

2.7

YUV Block

The TV video input module is used to interface external TV video decoder chip. It handles VESA

Video Interface Port(VIP) 8-bit/16-bit YCBCR, VMI/ ITU-R Recommendation 656 (CCIR656) YCBCR

and double clock edge input RGB data formats. It extracts embedded sync timing and converts data

into RGB color space. All the functions in this module are controlled by the system microcontroller

through I2C registers.

The following table describes the different pin configurations for YUV/RGB digital input.

X = don’t care

Mode

YUV[7:0]

TCON[3:0]

TCON[7:4]

CCIR656

DATA[7:0]

VMI

DATA[7:0]

{HREF, VREF, VACTIVE, X}

VIP 8b

DATA[7:0]

VIP 16b

DATA[7:0]

DATA[11:8]

DATA[15:12]

RGB Posedge

BLUE[7:0]

GREEN[3:0]

{HSYNC,VSYNC,DE,X}

RGB Negedge

{RED[3:0],GREEN[7:4]}

RED[7:4]

{HSYNC,VSYNC,DE,X}

Table 11: YUV Registers (Sheet 1 of 2)

Addr

Mode

Bits

Default

Description

YUV_CTRL

0x0700

[7:6]

Reserved

R/W

[5]

0x0

0: Rising edge of clock

1: Falling edge of clock

R/W

[4]

0x0

Input Source of Color Space Converter

0: YUV pins

1: ADC

R/W

[3]

0x0

Color Space Converter Enable

R/W

[2]

0x0

Sync Decoder Enable

R/W

[1]

0x0

Sample Input Data Rate

0:1x

1: 2x

R/W

[0]

0x0

Status Reset

YUV_STATUS

0x0701

[7]

Reserved

R/W

[6]

0x0

SAV detected

R/W

[5]

0x0

EAV detected

R/W

[4]

0x0

ANC detected

R/W

[3]

0x0

TASK detected

R/W

[2]

0x0

FIELDID detected

R/W

[1]

0x0

HSYNC detected

R/W

[0]

0x0

VSYNC detected

Writing to this register will clear all bits.

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