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ADE3000T 数据表(PDF) 30 Page - STMicroelectronics

部件名 ADE3000T
功能描述  LCD Display Engines with Integrated DVI, ADC and YUV Ports
PDF  88 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3000T 数据表(HTML) 30 Page - STMicroelectronics

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Sync Retiming Block
ADE3XXX
30/88
2.8
Sync Retiming Block
The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into
the XCLK and INCLK domains.
For the XCLK domain, SRT has the following functionality:
q
Retimes all sync signals going to SMEAS into the XCLK domain.
q
Extracts vertical sync from composite sync signals (ahsync and acsync pins)
q
Divides clocks by 1024 for activity detection purposes.
q
Generates a delay-filtered version of vertical sync from a mux-selectable vertical sync source.
q
Generates a coast signal in the XCLK domain for the LLPLL.
YUV_INT
0x0702
[7:6]
Reserved
R/W
[5]
0x0
0: VIP 8b mode
1: VIP 16b mode (skip 1 clock after
every 6 valid data)
R/W
[4:2]
0x0
YUV data input format
0x2: YUV 16-bit
0x4: YUV 8-bit
0x6: RGB
all others: Reserved
R/W
[1]
0x0
0: C-Y
1: Y-C
R/W
[0]
0x0
0: Cr-Cb
1: Cb-Cr
Table 12: Sync Retiming Registers (Sheet 1 of 2)
Register Name
Addr
Mode
Bits
Default
Description
SRTXK_CSYNC_INV
0x01E0
[7:3]
0x0
Reserved
R/W
[2]
0x0
invert filtered vert sync signal
R/W
[1]
0x0
invert composite sync signal
R/W
[0]
0x0
invert SOG signal
SRTXK_SOG_THR_L
0x01E1
R/W
[7:0]
0x080
SOG vert sync extractor threshold [7:0]
SRTXK_SOG_THR_H
0x01E2
R/W
[7:4]
Reserved
[3:0]
SOG vert sync extractor threshold [11:8]
SRTXK_CSYNC_THR_L
0x01E3
R/W
[7:0]
0x080
composite sync vertical sync extractor
threshold [7:0]
SRTXK_CSYNC_THR_H
0x01E4
R/W
[7:4]
Reserved
[3:0]
composite sync vertical sync extractor
threshold [11:8]
Table 11: YUV Registers (Sheet 2 of 2)
Register Name
Addr
Mode
Bits
Default
Description



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