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ADE3000SXT 数据表(PDF) 31 Page - STMicroelectronics |
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ADE3000SXT 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 88 page  31/88 ADE3XXX Sync Retiming Block SRTXK_VSYNC_SEL 0x01E5 R/W [7:3] Reserved [2:0] 0x0 filtered vert sync source select 0x0: avsync pin 0x1: vsync from composite ahsync pin 0x2: vsync from composite acsync pin 0x3: Reserved 0x4: DVI vsync 0x5: YUV vsync 0x6 - 0x7: Reserved SRTXK_VSYNC_THR_L 0x01E6 R/W [7:0] 0x080 filtered vert sync delay [7:0] SRTXK_VSYNC_THR_H 0x01E7 R/W [7:4] Reserved R/W [3:0] filtered vert sync delay [11:8] SRTXK_COAST_VS_SEL 0x01E8 [7:4] 0x0 Reserved R/W [3] 0x0 coast signal trigger edge 0: posedge of selected vertical 1: negedge of selected vertical R/W [2:0] 0x0 source select for coast vert sync trigger 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: Reserved 0x4: DVI vsync 0x5: YUV vsync 0x6: srt vsync (filtered vsync) 0x7: Reserved SRTXK_COAST_RISE_L 0x01E9 R/W [7:0] 0x0 rising edge of coast, in XCLKs from vsync trigger SRTXK_COAST_RISE_M 0x01EA R/W [7:0] 0x0 SRTXK_COAST_RISE_H 0x01EB R/W [7:0] 0x0 SRTXK_COAST_FALL_L 0x01EC R/W [7:0] 0x0 falling edge of coast, in XCLKs from vsync trigger SRTXK_COAST_FALL_M 0x01ED R/W [7:0] 0x0 SRTXK_COAST_FALL_H 0x01EE R/W [7:0] 0x0 SRTIK_HS_CTRL 0x01F0 [7:3] 0x0 Reserved R/W [2] 0x0 Resample clock edge to transfer hsync into the INCLK domain; depends on LLK phase offset value. 0: posedge INCLK 1: negedge INCLK R/W [1:0] 0x0 horz sync source select for resampling into the INCLK domain 0x0: LLPLL lock sync (normal) 0x1: ahsync pin 0x2: acsync pin 0x3: Reserved SRTIK_VS_SEL 0x01F1 [7:2] 0x0 Reserved R/W [1:0] 0x0 vert sync source select for resampling 0x0: avsync pin 0x1: vsync from ahsync pin 0x2: vsync from acsync pin 0x3: srt vsync (filtered vsync) Table 12: Sync Retiming Registers (Sheet 2 of 2) Register Name Addr Mode Bits Default Description |
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