 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADE3000SXT 数据表(PDF) 54 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ADE3000SXT 数据表(HTML) 54 Page - STMicroelectronics |
|
|
54 / 88 page  Output Sequencer Block ADE3XXX 54/88 OSQ_VERTEN_DLY_O_H 0x0BCE [7:4] 0x0 Reserved R/W [3:0] 0x0 delay of the vert_enab signal to the reset of the horizontal and vertical counters, odd frame in interlace mode only [19:16] OSQ_VSYNC_SET_L 0x0BCF R/W [7:0] 0x0 vertical count at which vsync goes high [7:0] OSQ_VSYNC_SET_H 0x0BD0 [7:4] 0x0 Reserved R/W [3:0] 0x0 vertical count at which vsync goes high [11:8] OSQ_VSYNC_RST_L 0x0BD1 R/W [7:0] 0x0 vertical count at which vsync goes low [7:0] OSQ_VSYNC_RST_H 0x0BD2 [7:4] 0x0 Reserved R/W [3:0] 0x0 vertical count at which vsync goes low [11:8] OSQ_HSYNC_SET_L 0x0BD3 R/W [7:0] 0x0 horizontal count at which hsync goes high [7:0] OSQ_HSYNC_SET_H 0x0BD4 [7:4] 0x0 Reserved R/W [3:0] 0x0 horizontal count at which hsync goes high [11:8] OSQ_HSYNC_RST_L 0x0BD5 R/W [7:0] 0x0 horizontal count at which hsync goes low [7:0] OSQ_HSYNC_RST_H 0x0BD6 [7:4] 0x0 Reserved R/W [3:0] 0x0 horizontal count at which hsync goes low [11:8] OSQ_HENAB_SET_L 0x0BD7 R/W [7:0] 0x0 horizontal count at which enab goes high [7:0] OSQ_HENAB_SET_H 0x0BD8 [7:4] Reserved R/W [3:0] horizontal count at which enab goes high [11:8] value must be greater than 0x01C OSQ_HENAB_RST_L 0x0BD9 R/W [7:0] 0x0 horizontal count at which enab goes low [7:0] OSQ_HENAB_RST_H 0x0BDA [7:4] Reserved R/W [3:0] horizontal count at which enab goes low [11:8] OSQ_VENAB_SET_L 0x0BDB R/W [7:0] 0x0 vertical count at which enab goes high [7:0] OSQ_VENAB_SET_H 0x0BDC [7:4] 0x0 Reserved R/W [3:0] 0x0 vertical count at which enab goes high [11:8] OSQ_VENAB_RST_L 0x0BDD R/W [7:0] 0x0 vertical count at which enab goes low [7:0] OSQ_VENAB_RST_H 0x0BDE [7:4] 0x0 Reserved R/W [3:0] 0x0 vertical count at which enab goes low [11:8] OSQ_OUT_VCOUNT 0x0BDF R [7:0] 0x0 vertical counter /16 indicating the current frame position Table 19: Output Sequencer Registers (Sheet 2 of 2) Register Name Addr Mode Bits Default Description |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
