ADE3050SXT datasheet(15/88 Pages) STMICROELECTRONICS

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ADE3XXX

Global Control Block

GLBL_CLK_SRC_SEL_2

0x0002

[7]

0x0

Reserved

R/W

[6:4]

0x4

LLK CTRL CLK source

0x0: YUVCLK pin

0x1: SCLK freq synth

0x2: LLKPLL control clock (normal)

0x3: CLKIN pin

0x4: crystal clock

0x5: 0

0x6 - 0x7: Reserved

[3]

Reserved

R/W

[2:0]

0x4

LLK ZERO CLK source

0x0: YUVCLK pin

0x1: SCLK freq synth

0x2: LLKPLL zero clock (normal)

0x3: CLKIN pin

0x4: crystal clock

0x5: 0

0x6 - 0x7: Reserved

GLBL_CLK_INV

0x0003

[7]

0x0

Reserved

R/W

[6]

0x0

Invert YUV clock

R/W

[5]

0x0

Invert DVI detect clock

R/W

[4]

0x0

Invert ADC clock

R/W

[3]

0x0

Invert LLPLL zero clock

R/W

[2]

0x0

Invert LLPLL ctrl clock

R/W

[1]

0x0

Invert DOT clock

R/W

[0]

0x0

Invert input clock

GLBL_ANA_PWR

0x0005

[7:5]

0x0

Reserved

R/W

[4]

0x1

Blue ADC power down

R/W

[3]

0x1

Green ADC power down

R/W

[2]

0x1

Red ADC power down

R/W

[1]

0x1

DVI detect clock power down

R/W

[0]

0x1

DVI PLL power down

GLBL_XK_SRST

0x0006

[7:3]

0x0

Reserved

R/W

[2]

0x0

SMEAS block reset, synchronous to XCLK

R/W

[1]

0x0

SRT block reset, synchronous to XCLK

R/W

[0]

0x0

Frame sync block reset, synchronous to

XCLK

GLBL_I2C_CTRL

0x0007

[7:3]

0x0

Reserved

R/W

[2]

0x0

Disable I2C auto increment

R/W

[1]

0x0

SDA PMOS enable

R/W

[0]

0x0

Bypass I2C filter

GLBL_XTAL_CTRL

0x0008

[7:1]

0x0

Reserved

R/W

[0]

0x1

Crystal Oscillator Enable

Table 4: Global Registers (Sheet 2 of 4)

Addr.

Mode

Bits

Default

Description

ADE3050SXT 数据表(PDF) 15 Page - STMicroelectronics

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ADE3050SXT 数据表(PDF) 15 Page - STMicroelectronics

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