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ADE3050SXT 数据表(PDF) 50 Page - STMicroelectronics |
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ADE3050SXT 数据表(HTML) 50 Page - STMicroelectronics |
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50 / 88 page  Scaler Block ADE3XXX 50/88 SCL_THRES_OFFSET_L 0x0A13 R/W [7:0] 0x40 offset of the contrast amplification function [7:0] SCL_THRES_OFFSET_H 0x0A14 R/W [7:2] 0x0 Reserved R/W [1:0] 0x2 offset of the contrast amplification function [9:8] SCL_CBBYPASS 0x0A15 R/W [7:2] 0x0 Reserved R/W [1] 0x0 0: normal 1: TCON control of contrast amplification R/W [0] 0x0 0: contrast amplification enabled 1: bypass contrast amplification SCL_CON_CAL_SEL 0x0A16 [7:1] Reserved R/W [0] 0x0 0: context = max of RGB pk-pk 1: context = sum of RGB pk-pk SCL_TESTCON 0x0A17 [7:2] 6b contrast amplification test data R/W [1:0] 0x0 0x0, 0x3: normal 0x1: force input data into the contrast amplifiation function to bits [7:2] 0x2: force the output context data to be bits [5:2] SCL_LUT1 0x0A18 R/W [7:0] 0xFA sigmoidal function LUT entry 1, 8b 2’s complement SCL_LUT2 0x0A19 R/W [7:0] 0xF7 sigmoidal function LUT entry 2, 8b 2’s complement SCL_LUT3 0x0A1A R/W [7:0] 0xF7 sigmoidal function LUT entry 3, 8b 2’s complement SCL_LUT4 0x0A1B R/W [7:0] 0xFC sigmoidal function LUT entry 4, 8b 2’s complement SCL_LUT5 0x0A1C R/W [7:0] 0x2 sigmoidal function LUT entry 5, 8b 2’s complement SCL_LUT6 0x0A1D R/W [7:0] 0x0D sigmoidal function LUT entry 6, 8b 2’s complement SCL_LUT7 0x0A1E R/W [7:0] 0x17 sigmoidal function LUT entry 7, 8b 2’s complement SCL_LUT8 0x0A1F R/W [7:0] 0x21 sigmoidal function LUT entry 8, 8b 2’s complement SCL_LUT9 0x0A20 R/W [7:0] 0x28 sigmoidal function LUT entry 9, 8b 2’s complement SCL_LUT10 0x0A21 R/W [7:0] 0x2C sigmoidal function LUT entry 10, 8b 2’s complement SCL_LUT11 0x0A22 R/W [7:0] 0x2C sigmoidal function LUT entry 11, 8b 2’s complement SCL_LUT12 0x0A23 R/W [7:0] 0x28 sigmoidal function LUT entry 12, 8b 2’s complement SCL_LUT13 0x0A24 R/W [7:0] 0x21 sigmoidal function LUT entry 13, 8b 2’s complement SCL_LUT14 0x0A25 R/W [7:0] 0x17 sigmoidal function LUT entry 14, 8b 2’s complement Table 18: Scaler Block Registers (Sheet 2 of 3) Register Name Addr Mode Bits Default Description |
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