CS8420 datasheet(41/80 Pages) CIRRUS

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CS8420

DS245PP2

11.17 Channel Status Data Buffer Control (18)

BSEL

Selects the data buffer register addresses to contain User data or Channel Status data

0 - Data buffer address space contains Channel Status data (default)

1 - Data buffer address space contains User data

CBMR

Control for the first 5 bytes of channel status “E” buffer

0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data

(default)

1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data

DETCI

D to E C-data buffer transfer inhibit bit.

0 - Allow C-data D to E buffer transfers (default)

1 - Inhibit C-data D to E buffer transfers

EFTCI

E to F C-data buffer transfer inhibit bit.

0 - Allow C-data E to F buffer transfers (default)

1 - Inhibit C-data E to F buffer transfers

CAM

C-data buffer control port access mode bit

0 - One byte mode

1 - Two byte mode

CHS

Channel select bit

0 - Channel A information is displayed at the EMPH pin and in the receiver channel

status register. Channel A information is output during control port reads when

CAM is set to 0 (One Byte Mode)

1 - Channel B information is displayed at the EMPH pin and in the receiver channel

status register. Channel B information is output during control port reads when

CAM is set to 0 (One Byte Mode)

3210

BSEL

CBMR

DETCI

EFTCI

CAM

CHS

CS8420 数据表(PDF) 41 Page - Cirrus Logic

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