CS8420 datasheet(46/80 Pages) CIRRUS

46 / 80 page

CS8420

DS245PP2

13. SOFTWARE MODE - PIN DESCRIPTION

The above diagram and the following pin descriptions apply to software mode. In hardware

mode, some pins change their function as described in subsequent sections of this data sheet.

Fixed function pins are marked with a *, and will be described once in this section. Pins marked

with a + are used upon reset to select various start-up options, and require a pull-up or pull-

down resistor.

Power Supply Connections:

VD+ - Positive Digital Power *

Positive supply for the digital section. Nominally +5V.

VA+ - Positive Analog Power *

Positive supply for the analog section. Nominally +5V. This supply should be as quiet as possible since

noise on this pin will directly affect the jitter performance of the recovered clock.

DGND - Digital Ground *

Ground for the digital section. DGND should be connected to the same ground as AGND.

AGND - Analog Ground *

Ground for the analog section. AGND should be connected to the same ground as DGND.

Clock Related Pins:

OMCK - Output Section Master Clock Input

Output section master clock input. The frequency must be 256x, 384x, or 512x the output sample rate

(Fso).

RMCK - Input Section Recovered Master Clock Output

Input section recovered master clock output. Will be at a frequency of 128x or 256x the input sample

rate (Fsi).

FILT - PLL Loop Filter *

An RC network should be connected between this pin and ground. Recommended schematic and

component values are given in the Receiver section of this data sheet.

CS8420 数据表(PDF) 46 Page - Cirrus Logic