CS8420 datasheet(45/80 Pages) CIRRUS

45 / 80 page

CS8420

DS245PP2

12.4

Synchronization of Multiple CS8420s

The serial audio output ports of multiple CS8420s

can be synchronized by sharing the same master

clock, OSCLK, OLRCK, and RST line and ensur-

ing that all devices leave the reset state on the same

master clock falling edge. Either all the ports need

to be in slave mode, or one can be set as a master.

The AES3 transmitters may be synchronized by

sharing the same master clock, TCBL, and RST

signals, and all devices leave the reset state on the

same master clock falling edge. The TCBL pin is

used to synchronize multiple CS8420 AES3 trans-

mitters at the channel status block boundaries. One

CS8420 must have its TCBL set to master; the oth-

ers must be set to slave TCBL. Alternatively,

TCBL can be derived from some external logic, in

which case all the CS8420 devices should be set to

slave TCBL.

12.5

Extended Range Sample Rate

Conversion

For handling sampling rate conversion ratios great-

er than 3:1 or less than 1:3, the user can use a cas-

cade of two devices. The product of the conversion

ratio of the two devices should equal the target con-

version ratio.

CS8420 数据表(PDF) 45 Page - Cirrus Logic