ST72F321 datasheet(78/189 Pages) STMICROELECTRONICS

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ST72321

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16-BIT TIMER (Cont’d)

10.4.3.5 One Pulse Mode

One Pulse mode enables the generation of a

pulse when an external event occurs. This mode is

selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1

function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-

mula in the opposite column).

2. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin

must be configured as floating input).

3. Select the following in the CR2 register:

– Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

– Set the OPM bit.

– Select the timer clock CC[1:0] (see Table 16

Clock Control Bits).

Then, on a valid event on the ICAP1 pin, the coun-

ter is initialized to FFFCh and OLVL2 bit is loaded

on the OCMP1 pin, the ICF1 bit is set and the val-

ue FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge

occurs, an interrupt can be generated if the ICIE

bit is set.

Clearing the Input Capture interrupt request (i.e.

clearing the ICFi bit) is done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

The OC1R register value required for a specific

timing application can be calculated using the fol-

lowing formula:

Where:

= Pulse period (in seconds)

fCPU

= CPU clock frequency (in hertz)

PRESC = Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 16

Clock Control Bits)

If the timer clock is an external clock the formula is:

Where:

= Pulse period (in seconds)

fEXT

= External timer clock frequency (in hertz)

When the value of the counter is equal to the value

of the contents of the OC1R register, the OLVL1

bit is output on the OCMP1 pin, (See Figure 52).

Notes:

1. The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an

Output Compare interrupt.

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform

input capture (ICF2 can be set and IC2R can be

loaded) but the user must take care that the

counter is reset each time a valid edge occurs

on the ICAP1 pin and ICF1 can also generates

interrupt if ICIE is set.

5. When one pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and

OCF2 can be used to indicate a period of time

has been elapsed but cannot generate an out-

put waveform because the level OLVL2 is dedi-

cated to the one pulse mode.

event occurs

Counter

= OC1R

OCMP1 = OLVL1

When

on ICAP1

One pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

ICR1 = Counter

OCiR Value =

t * fCPU

PRESC

- 5

OCiR =

t * fEXT -5

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