ST72F321 datasheet(80/189 Pages) STMICROELECTRONICS

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ST72321

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16-BIT TIMER (Cont’d)

10.4.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the

generation of a signal with a frequency and pulse

length determined by the value of the OC1R and

OC2R registers.

Pulse Width Modulation mode uses the complete

Output Compare 1 function plus the OC2R regis-

ter, and so this functionality can not be used when

PWM mode is activated.

In PWM mode, double buffering is implemented on

the output compare registers. Any new values writ-

ten in the OC1R and OC2R registers are taken

into account only at the end of the PWM period

(OC2) to avoid spikes on the PWM output pin

(OCMP1).

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the

formula in the opposite column.

2. Load the OC1R register with the value corre-

sponding to the period of the pulse if (OLVL1=0

and OLVL2=1) using the formula in the oppo-

site column.

3. Select the following in the CR1 register:

– Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with the OC1R register.

– Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful

comparison with the OC2R register.

4. Select the following in the CR2 register:

– Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

– Set the PWM bit.

– Select the timer clock (CC[1:0]) (see Table 16

Clock Control Bits).

If OLVL1=1 and OLVL2=0 the length of the posi-

tive pulse is the difference between the OC2R and

OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen

on the OCMP1 pin.

The OCiR register value required for a specific tim-

ing application can be calculated using the follow-

ing formula:

Where:

= Signal or pulse period (in seconds)

fCPU

= CPU clock frequency (in hertz)

PRESC = Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 16 Clock

Control Bits)

If the timer clock is an external clock the formula is:

Where:

= Signal or pulse period (in seconds)

fEXT

= External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter

to be initialized to FFFCh (See Figure 53)

Notes:

1. After a write instruction to the OCiHR register,

the output compare function is inhibited until the

OCiLR register is also written.

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output

Compare interrupt is inhibited.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a

timer interrupt if the ICIE bit is set and the I bit is

cleared.

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected to the timer. The ICAP2 pin can be used

to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take

care that the counter is reset each period and

ICF1 can also generates interrupt if ICIE is set.

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

Counter

OCMP1 = OLVL2

Counter

= OC2R

OCMP1 = OLVL1

When

= OC1R

Pulse Width Modulation cycle

Counter is reset

to FFFCh

ICF1 bit is set

OCiR Value =

t * fCPU

PRESC

- 5

OCiR =

t * fEXT -5

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