ST72F321 datasheet(107/189 Pages) STMICROELECTRONICS

107 / 189 page

ST72321

107/189

SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.9 Clock Deviation Causes

The causes which contribute to the total deviation

are:

–DTRA: Deviation due to transmitter error (Local

oscillator error of the transmitter or the trans-

mitter is transmitting at a different baud rate).

–DQUANT: Error due to the baud rate quantisa-

tion of the receiver.

–DREC: Deviation of the local oscillator of the

receiver: This deviation can occur during the

reception of one complete SCI message as-

suming that the deviation has been compen-

sated at the beginning of the message.

–DTCL: Deviation due to the transmission line

(generally due to the transceivers)

All the deviations of the system should be added

and compared to the SCI clock tolerance:

DTRA + DQUANT + DREC + DTCL < 3.75%

10.6.4.10 Noise Error Causes

See also description of Noise error in Section

10.6.4.3.

Start bit

The noise flag (NF) is set during start bit reception

if one of the following conditions occurs:

1. A valid falling edge is not detected. A falling

edge is considered to be valid if the 3 consecu-

tive samples before the falling edge occurs are

detected as '1' and, after the falling edge

occurs, during the sampling of the 16 samples,

if one of the samples numbered 3, 5 or 7 is

detected as a “1”.

2. During sampling of the 16 samples, if one of the

samples numbered 8, 9 or 10 is detected as a

“1”.

Therefore, a valid Start Bit must satisfy both the

above conditions to prevent the Noise Flag getting

set.

Data Bits

The noise flag (NF) is set during normal data bit re-

ception if the following condition occurs:

– During the sampling of 16 samples, if all three

samples numbered 8, 9 and10 are not the same.

The majority of the 8th, 9th and 10th samples is

considered as the bit value.

Therefore, a valid Data Bit must have samples 8, 9

and 10 at the same value to prevent the Noise

Flag getting set.

Figure 64. Bit Sampling in Reception Mode

RDI LINE

Sample

clock

12345678910

sampled values

One bit time

6/16

7/16

ST72F321 数据表(PDF) 107 Page - STMicroelectronics

ST72F321 数据表(HTML) 107 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载