PI2007 datasheet(2/19 Pages) VICOR

2 / 19 page

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Picor Corporation • picorpower.com

PI2007

Rev 1.3

Page 2 of 19

Pin Description

Pin Name

Number

Description

PGND

Gate Turn Off Switch Return: This pin is the high current return path for the gate driver

during turn off. Connect this pin to the low side of the VC coupling capacitor and SGND.

GATE

Gate Drive Output: This pin drives the gate of the external N-channel MOSFET. Under

normal operating conditions and when VSP-SN > 6mV, the GATE pin pulls high to

approximately 2*VC with respect to the SGND pin. The controller turns the gate off

during a reverse current fault that is below the reverse voltage threshold (-6mV) and

when VC is in Under Voltage (7.15V).

Controller Input Supply: This pin is the supply pin for the control circuitry and gate

driver. Connect a

1μF capacitor between the VC pin and the SGND pin. Voltage on this

pin is regulated to 11.7V with respect to SGND by an internal shunt regulator. For high

voltage supply applications connect a shunt resistor between the SGND and PGND pins

and the supply return, as shown in Figure 2.

SGND

VC Return: This pin is the return (ground) for the control circuitry. Connect this pin to

the low side of VC decoupling capacitor.

Controller Input Supply With Limiting Resistor: This pin is connected internally to VC

through a

420Ω resistor needed for Bus voltages greater than 10V and less than 14V.

Leave this pin open if unused.

Positive Sense Input: Connect SP pin to the Source pin of the external N-channel

MOSFETs. The polarity of the voltage difference between SP and SN provides an

indication of current flow direction through the MOSFET.

7, 10

Not Connected: Leave pins floating.

Negative Sense Input: Connect SN to the Drain pin of the external N-channel MOSFET.

The polarity of the voltage difference between SP and SN provides an indication of

current flow direction through the MOSFET.

Fault Status Output: This open collector pin pulls low to indicate one of the several

potential fault conditions may exist. The FT pin will pull low after a reverse or forward

fault has been detected

with a defined delay time (8μs). In addition, the FT pin will pull

low when the controller input voltage is below the VC under-voltage threshold VVC-SGND <

7V. When VVC-SGND > 7.15V and 6mV < VSP-SN < 275mV this pin clears (High). In high

voltage applications this output must be translated with reference to the system return

with external circuitry, see Figure 19. Leave this pin open if unused.

Package Pin-Outs

10 Lead DFN (3mm x 3mm)

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