PI2007 datasheet(5/19 Pages) VICOR

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Picor Corporation • picorpower.com

PI2007

Rev 1.3

Page 5 of 19

Functional Description:

The PI2007 Cool-ORing controller IC is designed to

drive single or parallel N-channel MOSFETs in high

side Active ORing applications.

The PI2007 used

with an external MOSFET can function as an ideal

ORing diode in the high side of a redundant power

system, significantly reducing power dissipation and

eliminating the need for heatsinking.

An N-channel MOSFET in the conduction path offers

extremely low on-resistance resulting in a dramatic

reduction

power

dissipation

versus

the

performance of a diode used in conventional ORing

applications due to its high forward voltage drop.

This can allow for the elimination of complex heat

sinking

and

other

thermal

management

requirements.

Due to the inherent characteristics of the MOSFET,

current will flow in the forward and reverse directions

while the gate remains above the gate threshold

voltage. Ideal ORing applications should not allow

reverse current flow, so the controller has to be

capable of very fast and accurate detection of

reverse current caused by input power source

failures, and very fast turn off of the gate of the

MOSFET. Once the gate voltage falls below the gate

threshold, the MOSFET is off and the body diode will

be reverse biased preventing reverse current flow

and subsequent excessive voltage droop on the

redundant bus.

Differential Amplifier:

The PI2007 integrates a high-speed low offset

voltage differential amplifier to sense the difference

between the Sense Positive (SP) pin voltage and

Sense Negative (SN) pin voltage with high accuracy.

The amplifier output is connected to the Reverse

and Forward comparators.

Reverse Current Comparator: RVS

The reverse current comparator provides the critical

function in the controller, detecting negative voltage

caused by reverse current. When the SN pin is 6mV

higher than the SP pin, the reverse comparator will

force the gate discharge circuit to turn off the

MOSFETs in typically 80ns.

The reverse comparator will hold the gate low until

the SP pin is 6mV higher than the SN pin.

The

reverse comparator hysteresis is shown in Figure 3.

Figure 3: Reverse comparator hysteresis: VSP - VSN

There is a bias current path from SN to SP during

the reverse fault condition. The bias current is

proportional to the voltage between SN and SP.

The maximum SN pin bias current is 9mA when

VSN=80V and VSP=0V and assumes that the

MOSFET is in the off condition. Refer to Figure 15

in the Application Information section for more

details.

Forward Voltage Comparator: FWD

The FWD comparator detects when a forward

voltage condition exists and SP is above 275mV

(typical) positive with respect to SN. When SP-SN is

more than 275mV, the FWD comparator will assert

the Gate Status low to report a fault condition.

VC and Internal Voltage Regulator:

The PI2007 has a separate input VC that provides

power to the control circuitry, charge pump and gate

driver. An internal regulator clamps the VC voltage

(VVC-SGND) to 11.7V.

The internal regulator circuit has a comparator to

monitor the VC voltage and pulls the GATE pin low

when the VC is lower than the VC Under-Voltage

Threshold.

In 12V Bus applications (10V to 14V) the VR input

pin can be connected to the input voltage eliminating

the need for an external limiter. An i

nternal 420Ω

resistor is connected between the VR pin and the

internal regulator VC pin.

Charge Pump:

The PI2007 has an integrated charge pump that

approximately

doubles

the

voltage

with

reference to the SGND pin, to drive the N-Channel

MOSFET gate to a voltage higher than the input

voltage at 15µA minimum source current.

Gate Driver:

The gate driver (GATE) output is configured to drive

an external N-channel MOSFET. In the high state,

the gate driver applies a 20µA typical current source

to the MOSFET gate from the integrated charge

pump. The Charge Pump voltage is limited to

2*(VVC –VSGND -1V).

When a reverse current fault is initiated, the gate

driver pulls the GATE pin low to the PGND pin and

discharges the MOSFET gate with 4A typical peak

capability.

Fault Indication:

The FT pin is an open collector NPN that will be

pulled low when the Gate pin is low. The FT pin is

also pulled low when VVC-SGND is below UVLO or

during the following fault conditions as indicated in

the table below:

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