AS4SD16M16 datasheet(6/52 Pages) MICROSS

6 / 52 page

SDRAM

AS4SD16M16

Rev. 2.6 04/13/15

Micross Components reserves the right to change products or specifications without notice.

CAS Latency

The CAS latency is the delay, in clock cycles, between

the registration of a READ command and the availability of

the first piece of output data. The latency can be set to two or

three clocks.

If a READ command is registered at clock edge n, and the

latency is m clocks, the data will be available by clock edge

n + m. The DQs will start driving as a result of the clock edge

one cycle earlier (n + m - 1), and provided that the relevant

access times are met, the data will be valid by clock edge n +

m. For example, assuming that the clock cycle time is such

that all relevant access times are met, if a READ command is

registered at T0 and the latency is programmed to two clocks,

the DQs will start driving after T1 and the data will be valid by

T2, as shown in Figure 2. Table 2 below indicates the operating

frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting M7 and

M8 to zero; the other combinations of values for M7 and M8

are reserved for future use and/or test modes. The programmed

burst length applies to both READ and WRITE bursts.

Test modes are reserved states should not be used because

unknown operation or incompatibility with future versions may

result.

Write Burst Mode

When M9=0, the burst length programmed via M0-M2

applies to both READ and WRITE bursts; when M9=1, the

programmed burst length applies to READ bursts, but write

accesses are single-location (non-burst) accesses.

FIGURE 2: CAS Latency

TABLE 2: CAS Latency

CAS

LATENCY = 2

CAS

LATENCY = 3

-75

<100

<133

SPEED

ALLOWABLE OPERATING

FREQUENCY (MHz)

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