AS4SD16M16 datasheet(9/52 Pages) MICROSS

9 / 52 page

SDRAM

AS4SD16M16

Rev. 2.6 04/13/15

Micross Components reserves the right to change products or specifications without notice.

OPERATION

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a

bank within the SDRAM, a row in that bank must be “opened.”

This is accomplished via theACTIVE command, which selects

both the bank and the row to be activated (see Figure 3).

After opening a row (issuing an ACTIVE command), a

READ or WRITE command may be issued to that row, sub-

ject to the t

RCD specification. tRCD (MIN) should be divided

by the clock period and rounded up to the next whole number

to determine the earliest clock edge after the ACTIVE com-

mand on which a READ or WRITE command can be entered.

For example, a tRCD specification of 20ns with a 125 MHz

clock (8ns period) results in 2.5 clocks, rounded to 3. This is

reflected in Figure 4, which covers any case where 2 < t

RCD

(MIN)/

CK < 3. (The same procedure is used to convert

other specification limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row in the

same bank can only be issued after the previous active row

has been “closed” (precharged). The minimum time interval

between successive ACTIVE commands to the same bank is

defined by t

RC.

A subsequent ACTIVE command to another bank can be

issued while the first bank is being accessed, which results in

a reduction of total row-access overhead. The minimum time

interval between successive ACTIVE commands to different

banks is defined by t

RRD.

FIGURE 3: Activating a Specific Row

in a Specific Bank

FIGURE 4: Example - Meeting t

RCD (MIN) When 2 < tRCD (MIN)/ tCK < 3

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