 2014 Microchip Technology Inc.

DS20005164C-page 9

SST25WF080B

5.0

INSTRUCTIONS

Instructions are used to read, write (Erase and Pro-

gram), and configure the SST25WF080B devices. The

instruction bus cycles are 8 bits each for commands

(Op Code), data, and addresses. The Write-Enable

(WREN) instruction must be executed prior to Sector-

Erase, Block-Erase, Page-Program, Write-Status-Reg-

ister, or Chip-Erase instructions. The complete instruc-

tions are provided in Table 5-1. All instructions are

synchronized off a high-to-low transition of CE#. Inputs

will be accepted on the rising edge of SCK starting with

the most significant bit. CE# must be driven low before

an instruction is entered and must be driven high after

the last bit of the instruction has been shifted in (except

for Read, Read-ID, and Read-Status-Register instruc-

tions). Any low-to-high transition on CE#, before receiv-

ing the last bit of an instruction bus cycle, will terminate

the instruction in progress and return the device to

standby mode. Instruction commands (Op Code),

addresses, and data are all input from the most signifi-

cant bit (MSB) first.

TABLE 5-1:

DEVICE OPERATION INSTRUCTIONS

Instruction

Description

1. One bus cycle is eight clock periods.

Address

Dummy

Cycle(s)

Data

Cycle(s)

Maximum

Frequency

Read

Read Memory

0000 0011b (03H)

3

0

1 to



30 MHz

High-Speed Read

Read Memory at Higher

Speed

0000 1011b (0BH)

3

1

1 to



40 MHz

Fast-Read Dual-

Output

Read Memory with Dual Out-

put

0011 1011b (3BH)

3

3. One bus cycle is four clock periods in Dual Operation

1 to

3

Fast-Read Dual I/O Read Memory with Dual

Address Input and Data Output

1011 1011b (BBH)

33

13

1 to

3

4 KByte Sector-

Erase 4 KByte of memory array 0010 0000b (20H)

1101 0111b (D7H)

30

0

64 KByte Block-

Erase 64 KByte block

of memory array

1101 1000b (D8H)

3

0

0

Chip-Erase

Erase Full Memory Array

0110 0000b (60H)

or

1100 0111b (C7H)

00

0

Page-Program

To program up to 256 Bytes

0000 0010b (02H)

3

0

1 to 256

6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

Read-Status-Register

0000 0101b (05H)

0

0

1 to



WRSR

Write-Status-Register

0000 0001b (01H)

0

0

1

WREN

Write-Enable

0000 0110b (06H)

0

0

0

WRDI

Write-Disable

0000 0100b (04H)

0

0

0

7. Device ID is read after three dummy address bytes. The Device ID output stream is continuous until terminated by a low-to-

high transition on CE#.

8. The instructions Release from Deep Power down and Read-ID are similar instructions (ABH). Executing Read-ID requires

the ABH instruction, followed by 24 dummy address bits to retrieve the Device ID. Release from Deep Power-Down only

requires the instruction ABH.

Read-ID

1010 1011b (ABH)

3

0

1 to



JEDEC-ID

JEDEC ID Read

1001 1111b (9FH)

0

0

4 to



DPD

Deep Power-Down Mode

1011 1001b (B9H)

0

0

0

RDPD8

Release from Deep Power-

Down or Read ID

1010 1011b (ABH)

0

0

0