SST25WF080B datasheet(17/39 Pages) MICROCHIP

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DS20005164C-page 17

SST25WF080B

5.12

Write-Status-Register (WRSR)

The Write-Status-Register instruction writes new val-

ues to the BP0, BP1, BP2, TB, and BPL bits of the sta-

tus register. CE# must be driven low before the

command sequence of the WRSR instruction is

entered and driven high before the WRSR instruction is

executed. Poll the BUSY bit in the Software Status reg-

ister, or wait TWRSR, for the completion of the internal

self-timed Write-Status-Register cycle. See Figure 5-

12 for WREN and WRSR instruction sequences and

Figure 6-11 for the WRSR flow chart.

Executing the Write-Status-Register instruction will be

ignored when WP# is low and BPL bit is set to ‘1’. When

the WP# is low, the BPL bit can only be set from ‘0’ to

‘1’ to lock-down the status register, but cannot be reset

from ‘1’ to ‘0’. When WP# is high, the lock-down func-

tion of the BPL bit is disabled and the BPL, BP0, BP1,B

P2, and TB bits in the status register can all be

changed. As long as BPL bit is set to ‘0’ or WP# pin is

driven high (VIH) prior to the low-to-high transition of the

CE# pin at the end of the WRSR instruction, the bits in

the status register can all be altered by the WRSR

instruction. In this case, a single WRSR instruction can

set the BPL bit to ‘1’ to lock down the status register as

well as altering the BP0, BP1, BP2, and TB bits at the

same time. See Table 4-1 for a summary description of

WP# and BPL functions.

FIGURE 5-12:

WRITE-ENABLE (WREN) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE

25164 F20.0

MODE 3

HIGH IMPEDANCE

MODE 0

STATUS

7 65 4321 0

MSB

MODE 3

SCK

CE#

MODE 0

0 1 2 3 45 6 7

0 1 2 3 45 6 7 8

10 11 12 13 14 15

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