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STM32F413RHT6 数据表(PDF) 165 Page - STMicroelectronics |
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STM32F413RHT6 数据表(HTML) 165 Page - STMicroelectronics |
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165 / 207 page  DocID029162 Rev 2 165/207 STM32F413xG/H Electrical characteristics 174 Synchronous waveforms and timings Figure 57 through Figure 60 represent synchronous waveforms and Table 95 through Table 98 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F446 reference manual: RM0390) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Table 93. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 4 * THCLK - 1 4 * THCLK + 1 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK - 1 THCLK + 0.5 tw(NWE) FSMC_NWE low time 2 * THCLK - 0.5 2 * THCLK - 0.5 th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK - 0.5 - tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 0 0.5 tw(NADV) FSMC_NADV low time THCLK THCLK + 1 th(AD_NADV) FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK + 0.5 - th(A_NWE) Address hold time after FSMC_NWE high THCLK + 0.5 - th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK - 0.5 - tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 tv(Data_NADV) FSMC_NADV high to Data valid - THCLK + 2.5 th(Data_NWE) Data hold time after FSMC_NWE high THCLK - 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 94. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 9 * THCLK - 1 9 * THCLK + 1 ns tw(NWE) FSMC_NWE low time 7 * THCLK - 0.5 7 * THCLK + 0.5 tsu(NWAIT_NE) FSMC_NWAIT valid before FSMC_NEx high 6 * THCLK + 2 - th(NE_NWAIT) FSMC_NEx hold time after FSMC_NWAIT invalid 4 * THCLK - 1 - 1. CL = 30 pF. 2. Based on characterization, not tested in production. |
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