AD1812

REV. 0

–5–

TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)

Parameter

Symbol

Min

Typ

Max

Units

IOW

/IOR Strobe Width

100

ns

IOW

/IOR Rising to IOW/IOR Falling

80

ns

Write Data Setup to IOW Rising

10

ns

IOR

Falling to Valid Read Data

40

ns

AEN Setup to IOW/IOR Falling

10

ns

AEN Hold from IOW/IOR Rising

0ns

Adr Setup to IOW/IOR Falling

10

ns

Adr Hold from IOW/IOR Rising

10

ns

DACK

Rising to IOW/IOR Falling

20

ns

IOW

/IOR Rising to DACK Falling

0ns

DACK

Setup to IOW/IOR Falling

10

ns

Data Hold from IOR Rising

20

ns

Data Hold from IOW Rising

15

ns

DRQ Hold from IOW/IOR Falling

25

ns

DACK

Hold from IOW Rising

10

ns

DACK

Hold from IOR Rising

10

ns

*Guaranteed, not tested.

Specifications subject to change without notice.

General Notes

Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield

meaningful results for an additional device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add

up parameters to derive longer times. Note that all 8-bit DMA transfers occur on channels 0, 1, and 3, while all 16-bit DMA transfers occur on channels 5, 6, and 7.

DRQ

(0, 1, 3, 5, 6, 7)

DACK

(0, 1, 3, 5, 6, 7)

AEN

IOR

PC_D (7:0) /

PC_D (15:0)

PC_A (15:0)

Figure 1. PIO Read Cycle

DRQ

(0, 1, 3, 5, 6, 7)

DACK

(0, 1, 3, 5, 6, 7)

AEN

IOR

PC_D (7:0) /

PC_D (15:0)

Figure 3. DMA Read Cycle

DRQ

(0, 1, 3, 5, 6, 7)

DACK

(0, 1, 3, 5, 6, 7)

AEN

IOW

PC_D (7:0) /

PC_D (15:0)

PC_A (15:0)

Figure 2. PIO Write Cycle

DRQ

(0, 1, 3, 5, 6, 7)

DACK

(0, 1, 3, 5, 6, 7)

AEN

IOW

PC_D (7:0) /

PC_D (15:0)

Figure 4. DMA Write Cycle