AD1812

REV. 0

–13–

Table V. Plug and Play Registers (PNP Asserted)

Port Name

Location

Type

ADDRESS

0x279 (Printer Status Port)

Write-Only

WRITE_DATA 0xA79 (Printer Status Port + 0x800)

Write-Only

READ_DATA

Relocatable in Range 0x203 – 0x3FF

Read-Only

Table VI. Non-Plug and Play Registers (PNP Deasserted)

Port Name

Location

Type

ADDRESS

0x234

Write-Only

WRITE_DATA 0x235

Write-Only

READ_DATA

Relocatable in Range 0x203 – 0x3FF

Read-Only

PnP AD1812 (Card) Status

For cards in PnP mode (PnP_Enable asserted), the Plug and

Play ISA Specification describes how to transfer the AD1812

from its start-up state, “Wait For Key” State, to the configura-

tion state, “Config” State. In the configuration state, the I/O

ranges, interrupt channels, and DMA channels can be assigned.

For non-PnP operation, no initialization protocol is needed

because the card is locked in the configuration state.

Configuration Register Description

The following describes only the subset of PnP Registers that

are unique to the AD1812 or necessary for non-PnP operation.

All other PnP registers are described in the Plug and Play ISA

Specification.

A register is selected by performing an 8-bit I/O write to the

ADDRESS Port, followed by either a read from the READ_DATA

location or a write to the WRITE_DATA location. Successive

reads or writes to a single register can be done without rewriting

the ADDRESS register. The following are valid values for the

ADDRESS Port.

Table VII. PnP Address Port Registers

Address

Register Name

Value

Type

Description

RD_DATA Port 0x00

Write-Only Sets the value of the

READ_DATA Port.

Config Control

0x02

Write-Only Resets all logical devices.

Logical Device

0x07

Read/Write Selects current logical

Number

device.

Powerdown

0x20

Read/Write Manages power for

portions of the AD1812.

SOUND BLASTER EMULATION

Sound Blaster emulation is provided using a combination of the

embedded signal processor and dedicated hardware. All Sound

Blaster Pro version 2.01 functions are supported including

record. The hardware registers are fully implemented within the

AD1812, and the internal signal processor executes a command

controller to interpret all commands. The AD1812 uses the in-

ternal signal processor for decoding compressed files compatible

with Sound Blaster ADPCM.

MUSIC SYNTHESIZER EMULATION

The AD1812 includes an embedded signal processor based on

Analog Devices’ 16-bit fixed-point digital signal processor fam-

ily. All DSP instructions are ROM coded internally. The

music synthesis algorithm running on the signal processor emu-

lates the functions of industry standard OPL3 FM synthesizer

chips and delivers 20 voice polyphony. A dedicated pair of

∑∆

DACs converts the digitally synthesized music before mixing

with the AD1812 codec line output.

EuSynth-1+ was developed by EuPhonics, a research and prod-

uct development company that specializes in audio processing

and electronic music synthesis.

MPU-401 INTERFACE

The primary interface for communicating MIDI data to and

from the host PC is the emulated MPU-401 interface. The

MPU-401 interface includes has a built-in FIFO for communi-

cating to the host bus.

GAME PORT INTERFACE

An IBM-compatible game port interface is provided on-chip.

The game port is capable of supporting up to two joysticks.

Connecting the game port to a 15-pin D-sub connector requires

only a few capacitors and resistors. The AD1812 includes a

built-in game port timer.

MODEM INTERFACE

Asserting the MODEM_EN pin on the AD1812 provides chip

select, interrupt handling and address decoding for an external

modem chipset. The AD1812 decodes the modem ISA bus

address and issues a modem select on the MODEM_SEL pin.

Interrupts generated by the external modem are handled on the

MODEM_IRQ pin, converted to the assigned system interrupt

by the AD1812, and posted to the ISA bus. The modem inter-

face operates in a PnP or non-PnP enabled system.

PLUG AND PLAY (PnP)

The AD1812 can be used under PnP control or in a non-PnP

mode. The non-PnP registers mimic the PnP register set, ex-

cept for the user defined addresses for the PnP “ADDRESS”

and “WRITE_DATA” registers. The PnP registers are selected

by asserting the PnP pin. With the PnP pin deasserted, the

non-PnP registers are selected.

EuSynth-1+