STW4510 datasheet(29/57 Pages) STMICROELECTRONICS

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STw4510

Functional description

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Figure 8.

Block diagram of biasing and references of the device

3.3.1

Power supply domains

Table 13 lists the register bits and the signals that control the different STw4510 supply

domains for each supply.

Bandgap

All internal

references

Vref_18

All internal

biasing

Bias generator

Voltage reference control

Table 13.

Power supply domains

Supply

name

Description

Supply domains

HPM

Sleep

Power down

Vsdc1

Step-down

through vsdc1_prg[3:0] bits

then Vsdc1_sel[1:0] pads = 00

600 mA

Pwren signal

low (logical 0)

Vsdc2

Step-down

1.8 V

600 mA

10 mA

Pon signal (low

logical 0)

Vana1

LDO

1.5, 1.8, 2.5, 2.8 V

Vana1_sel[1:0] pads

150 mA

0.5 mA

pdn_vana1 bit,

en_vana1 bit

Vana2

LDO

1.8, 2.8, 3.0, 3.3V

Vana2_sel[1:0] pads

150 mA

pdn_vana2 bit,

en_vana2 bit

Vana3

LDO

1.8, 2.8, 3.0, 3.3V

Vana3_sel[1:0] pads

150 mA

pdn_vana3 bit,

en_vana3 bit

Vdig

LDO

1, 1.2, 1.5 V

Vdig_sel[1:0] pads

250 mA

en_vdig bit

Vmmc

LDO

1.8, 2.5, 2.85, 3 V

sel_vmmc[1:0] bits

150 mA

pdn_vmmc

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