Data Sheet

ADA4961

Parameter

Test Conditions/Comments

3.3 V Supply, Low

Power Mode

5.0 V Supply, High

Performance

Mode Operation

Min

Typ

Max

Min

Typ

Max

Unit

Third-Order Intermodulation

Distortion (IMD3)

spacing)

Maximum gain

−79

−85

dBc

Minimum gain

−77

−84

dBc

1 dB Compression Point (OP1dB)

16.4

18.8

dBm

Noise Figure (NF)

6.0

6.3

dB

Noise Density Referred to Output

(RTO)

−153

−153

dBm/Hz

AC PERFORMANCE, 2 GHz

Second Harmonic (HD2)

Maximum gain

−73

−75

dBc

Minimum gain

−76

−77

dBc

Third Harmonic (HD3)

Maximum gain

−65

−70

dBc

Minimum gain

−66

−69

dBc

Third-Order Intermodulation

Distortion (IMD3)

spacing)

Maximum gain

−64

−70

dBc

Minimum gain

−65

−70

dBc

1 dB Compression Point (OP1dB)

14.5

17.0

dBm

Noise Figure (NF)

8.8

9.0

dB

Noise Density Referred to Output

(RTO)

−150

−150

dBm/Hz

1

3.3 V high performance mode is not recommended because IMD performance degrades at hot temperatures.

TIMING SPECIFICATIONS

Table 3.

Parameter

Description

Min

Typ

Max

Unit

Serial Clock Period

50

ns

Setup Time Between Data and Rising Edge of SCLK

5

ns

Hold Time Between Data and Rising Edge of SCLK

5

ns

Setup Time Between Falling Edge of CS and SCLK

ns

Hold Time Between Rising Edge of CS and SCLK

ns

Minimum Period SCLK Can Be in Logic High State

25

ns

Minimum Period SCLK Can Be in Logic Low State

25

ns

Maximum Time Delay Between Falling Edge of SCLK and Output Data Validfor a Read Operation

ns

Maximum Time Delay Between CS Deactivationand SDIO Bus Return to High Impedance

ns

Timing Diagram

CS

SCLK

SDIO

Figure 2.

Rev. A | Page 5 of 24