ADA4961

Data Sheet

Rev. A | Page 16 of 24

THEORY OF OPERATION

DIGITAL INTERFACE OVERVIEW

The ADA4961 DGA has two digital gain control options: the

parallel control interface and the serial peripheral interface. The

desired gain control option is selected via the control pin,

MODE (see Table 7 for the truth table for the mode control

pins). The gain code is in a binary format. A voltage of 1.4 V to

3.3 V is required for a logic high.

Two pins are common to both gain control options: PM and

PWUP. PM allows the user to choose operation in low power

mode (logic high) or high performance mode (logic low).

PWUP is the power-up pin. The physical pins are shared

between the two interfaces, resulting in two different functions

per digital pin (see Table 2).

Table 7. Digital Control Interface Selection Truth Table

MODE

Interface

1

Parallel control

0

SPI

PARALLEL DIGITAL INTERFACE

The parallel digital interface uses five binary bits (Bits[A4:A0])

and a latch pin. The LATCH pin controls whether the input

data latch is transparent or latched. In transparent mode, gain

changes as input gain control bits change. In latched mode, gain

is determined by the latched gain setting and does not change

with changing input gain control bits.

SERIAL PERIPHERAL INTERFACE (SPI)

The SPI uses three pins: SDIO, A4/CLK, and A3/CS. The SPI

data register consists of eight bits, five gain control bits, two fast

attack attenuation step size address bits, and one read/write bit.

SDIO is the serial data input and output pin. The A4/CLK pin is

the serial clock, and A3/CS is the channel select pin.

DATA

LSB

MSB

LSB

MSB

D0

D1

D2

D3

D4

FA0

FA1

R/W

READ/

WRITE

FAST

ATTACK

GAIN CONTROL

Figure 39. 8-Bit SPI Register

To write to the SPI register, A3/CS must be pulled low and eight

clock pulses must be applied to A4/CLK. To read the SPI

register value, the R/W bit must be set high, A3/CS must be

pulled low, and the device must be clocked. After the register

has been read during the next eight clock cycles, the SPI

automatically enters write mode.

Fast Attack

The fast attack feature, accessible via the SPI, allows the gain to

reduce from its present setting by a predetermined step size.

Four different attenuation step sizes are available. The truth

table for fast attack is shown in Table 8.

Table 8. SPI 2-Bit Attenuation Step Size Truth Table

FA1

FA0

Step Size (dB)

0

0

1

0

1

2

1

0

4

1

1

8

SPI fast attack mode is controlled by the A2/FA pin. A logic

high on the A2/FA pin results in an attenuation that is selected

by Bits[FA1:FA0] in the SPI register.

Table 9. Gain Code vs. Voltage Gain Lookup Table

5-Bit Binary Gain Code

Voltage Gain (dB)

00000

15

00001

14

00010

13

00011

12

00100

11

00101

10

00110

9

00111

8

01000

7

01001

6

01010

5

01011

4

01100

3

01101

2

01110

1

01111

0

10000

−1

10001

−2

10010

−3

10011

−4

10100

−5

10101

−6