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LM64 数据表(PDF) 8 Page - National Semiconductor (TI) |
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LM64 数据表(HTML) 8 Page - National Semiconductor (TI) |
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8 / 29 page ![]() Notes Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise noted. Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > V+), the current at that pin should be limited to 5 mA. Parasitic components and/or ESD protection circuitry are shown in the table below, for the LM64’s pins, by an "X" when it exists. Care should be taken not to forward bias the parasitic diode, D1, present on pins D+ and D−. Doing so by more than 50 mV may corrupt temperature measurements. Pin Name PIN # D1 D2 D3 D4 D5 D6 R1 SNP ESD CLAMP GPIO1 1 X X X GPIO2 2 X X X GPIO3 3 X X X PWM 4 X X X V DD 5 X D+ 6 X X XXX X D− 7 X X XXX X T_Crit 8X X X X A0 12 X ALERT 14 X X X X TACH 15 X X X SMBDAT 16 X X X SMBCLK 17 X GPIO5 18 X X X GPIO4 19 X X X GPD1 20 X GPD2 21 X GPD3 22 X GPD4 23 X GPD5 24 X Note 4: Human body model, 100 pF discharged through a 1.5 k Ω resistor. Machine model, 200 pF discharged directly into each pin. See Figure 2 above for the ESD Protection Input Structure. Note 5: See the National Semiconductor Application Note AN-1187 for Thermal Resistance Junction-to-Ambient Temperature. Note 6: See the National Semiconductor Application Note AN-1187 for recommendations on SMT assembly using the LLP packages. Note 7: “Typicals” are at TA = 25˚C and represent most likely parametric norm. They are to be used as general reference values not for critical design calculations. Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 9: The supply current will not increase substantially with an SMBus transaction. Note 10: Local temperature accuracy does not include the effects of self-heating. The rise in temperature due to self-heating is the product of the internal power dissipation of the LM64 and the thermal resistance. See (Note 5) for the thermal resistance to be used in the self-heating calculation. Note 11: The output rise time is measured from (VIL max - 0.15 V) to (VIH min + 0.15 V). Note 12: The output fall time is measured from (VIH min + 0.15 V) to (VIL min - 0.15 V). Note 13: Holding the SMBData and/or SMBCLK lines Low for a time interval greater than tTIMEOUT will reset the LM64’s SMBus state machine, therefore setting SMBDAT and SMBCLK pins to a high impedance state. 20065505 FIGURE 2. ESD Protection Input Structure www.national.com 8 |
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