LM64 datasheet(21/29 Pages) NSC

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2.0 LM64 Registers (Continued)

Configuration Register

ADDRESS

Hex

Read/

Write

Bits

POR

Value

Name

Description

03 (09)

HEX CONFIGURATION REGISTER

03 (09)

R/W

ALERT

Mask

When this bit is a 0, ALERT interrupts are enabled.

When this bit is set to a 1, ALERT interrupts are masked, and the

ALERT pin is always in a high impedance (open) state.

STANDBY

When this bit is a 0, the LM64 is in operational mode, converting,

comparing, and updating the PWM output continuously.

When this bit is a 1, the LM64 enters a low power standby mode.

In STANDBY, continuous conversions are stopped, but a

conversion/comparison cycle may be initiated by writing any value to

the setting of bit 5 in this register.

PWM Disable

in STANDBY

When this bit is a 0, the LM64’s PWM output continues to output the

current fan control signal while in STANDBY.

When this bit is a 1, the PWM output is disabled (as defined by the

PWM polarity bit) while in STANDBY.

4:1

0000

These bits are unused and always set to 0.

RDTS Fault

Queue

0: an ALERT will be generated if any Remote Diode conversion result is

above the Remote High Set Point or below the Remote Low

Setpoint.

1: an ALERT will be generated only if three consecutive Remote Diode

conversions are above the Remote High Set Point or below the

Remote Low Setpoint.

Tachometer Count And Limit Registers

ADDRESS

Hex

Read/

Write

Bits

POR

Value

Name

Description

HEX TACHOMETER COUNT (MSB) and 46HEX TACHOMETER COUNT (LSB) REGISTERS (16 bits: Read LSB first to lock

MSB and ensure MSB and LSB are from the same reading)

Read

Only

7:0

N/A

Tachometer

Count (MSB)

These registers contain the current 16-bit Tachometer Count, representing

the period of time between tach pulses.

Note that the 16-bit tachometer MSB and LSB are reversed from the

16-bit temperature readings.

Read

Only

7:2

N/A

Tachometer

Count (LSB)

Read

Only

1:0

Tachometer

Edge Count

Bits

Edges Used

Tach_Count_Multiple

00:

Reserved - do not use

01:

10:

11:

Note: If PWM_Clock_Select = 360 kHz, then Tach_Count_Multiple = 1

regardless of the setting of these bits.

HEX TACHOMETER LIMIT (MSB) and 48HEX TACHOMETER LIMIT (LSB) REGISTERS

R/W

7:0

0xFF

Tachometer

Limit MSB)

These registers contain the current 16-bit Tachometer Count, representing

the period of time between tach pulses. Fan RPM = (f * 5,400,000) /

(Tachometer Count), where f = 1 for 2 pulses/rev fan; f = 2 for 1 pulse/rev

fan; and f = 2/3 for 3 pulses/rev fan. See the Applications Notes section

for more tachometer information. Note that the 16-bit tachometer MSB and

LSB are reversed from the 16 bit temperature readings.

R/W

7:2

0xFF

Tachometer

Limit (LSB)

R/W

1:0

[Reserved]

Not Used.

LM64 数据表(PDF) 21 Page - National Semiconductor (TI)

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