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ADA4817-2ACPZ-R2 数据表(PDF) 18 Page - Analog Devices |
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ADA4817-2ACPZ-R2 数据表(HTML) 18 Page - Analog Devices |
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18 / 25 page ![]() ADA4817-1/ADA4817-2 Data Sheet Rev. C | Page 18 of 25 LEAKAGE CURRENTS Poor PCB layout, contaminants, and the board insulator material can create leakage currents that are much larger than the input bias current of the ADA4817-1/ADA4817-2. Any voltage differential between the inputs and nearby runs sets up leakage currents through the PCB insulator, for example, 1 V/ 100 GΩ = 10 pA. Similarly, any contaminants, such as skin oils on the board, can create significant leakage. To reduce leakage significantly, put a guard ring (shield) around the inputs and input leads that are driven to the same voltage potential as the inputs. This way there is no voltage potential between the inputs and surrounding area to set up any leakage currents. For the guard ring to be completely effective, it must be driven by a relatively low impedance source and it must completely surround the input leads on all sides (above and below) while using a multilayer board. Another effect that can cause leakage currents is the charge absorption of the insulator material itself. Minimizing the amount of material between the input leads and the guard ring helps to reduce the absorption. In addition, low absorption materials, such as Teflon® or ceramic, can be necessary in some instances. INPUT CAPACITANCE Along with bypassing and ground, high speed amplifiers can be sensitive to parasitic capacitance between the inputs and ground. A few picofarads of capacitance reduces the input impedance at high frequencies, in turn increasing the gain of the amplifier, causing peaking of the frequency response or even oscillations if severe enough. It is recommended to place the external passive components connected to the input pins as close as possible to the inputs to avoid parasitic capacitance. The ground and power planes must be kept at a small distance from the input pins on all layers of the board. INPUT-TO-INPUT/OUTPUT COUPLING To minimize capacitive coupling between the inputs and outputs, ensure that the output signal traces are not parallel with the inputs. In addition, ensure that the input traces are not close to each other. A minimum of 7 mils between the two inputs is recommended. |
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