09/01/15

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5W, QI WIRELESS POWER RECEIVER WITH INTEGRATED RECTIFIER AND LDO OUTPUT

P9025AC DATASHEET

Application Information

External Components

The P9025AC requires a minimum number of external

components for proper operation, as indicated in the

Reference schematic.

LDO

(PGND). Ceramic capacitors are recommended for their lower

ESR and small profile.

The P9025AC has an internal LDO regulator that must be

pin with a close GND connection.

Output Capacitor

A 0.1µF and a 4.7µF capacitors in parallel must be connected

from this pin to ground (PGND). The trace should be made as

short as practical for maximum device performance. Since the

LDO has been designed to function with very low ESR

capacitors, a ceramic capacitor is recommended for best

performance. For better transient response increase the total

amount of output capacitance. For 1-Amp load steps, an

output capacitance of at least 10µF is recommended.

NC and DNC Pins

NC pins that are indicated as “Not Internally Connected”

should be soldered to the PCB ground plane to improve

thermal performance with multiple vias exiting the bottom side

of the PCB. This improves heat flow away from the package

and minimizes package thermal gradients.

DNC pins that are indicated as “Internally connected” must be

left floating.

PCB Layout Considerations

For optimum device performance and lowest output phase

noise, IDT recommends that customers copy the reference

layout used in the P9025AC-R-EVK reference kit. More

information and layout files can be found at

http://www.idt.com/P9025AC-R-EVK.

Additional layout guidelines can be found in application note

AN-889 P9025AC Layout Guidelines. Users are encouraged

to read this document prior to starting a board design.

Power Dissipation and Thermal Requirements

The P9025AC is offered in a VFQFPN-32 package which has

a maximum power dissipation capability of about 1.9W. The

maximum power dissipation is determined by the number of

thermal vias between the package and the printed circuit

board, combined with the ability of the board to ultimately

transfer the thermal energy into the ambient environment. The

maximum power dissipation is defined by the dies specified

junction temperature rises when the heat generated by the

device's power dissipation goes through the package thermal

resistance. The VFQFPN package offers a typical thermal

PCB layout and surrounding devices are optimized as

described in application note AN-889 P9025AC Layout

Guidelines.

Thermal Overload Protection

The P9025AC integrates thermal overload shutdown circuitry

to prevent damage resulting from excessive thermal stress

that may be encountered under fault conditions. This circuitry

will shut down and reset the device if the die temperature

exceeds 150°C. To allow the maximum load current on each

regulator and the synchronous rectifier, and to prevent thermal

overload, it is important to ensure that the heat generated by

the P9025AC is dissipated efficiently into the PCB and

environment

End of Charge (EOC)

In the event of thermal shutdown (150°C), EN, CHG_END or

TEOP pins assertion the device turns off the LDO and

continually sends End Of Power (EOP) packets until the

transmitter removes the power and the rectifier voltage on the

receiver side drops below the UVLO threshold.

Special Notes

32-VFQFPN Package Assembly

Note 1

: Unopened Dry Packaged Parts have a one year shelf

life.

Note 2

: The HIC indicator card for newly-opened Dry

Packaged Parts should be checked. If there is any moisture

content, the parts must be baked for a minimum of 8 hours at

125°C within 24 hours of the assembly reflow process.