P9242-R Datasheet

© 2016 Integrated Device Technology, Inc

18

December 16, 2016

8. Communication Interface

8.1

Modulation/Communication

The WPC-1.2.2 extended power profile specification uses two-way communication for power transfer: receiver-to-transmitter and transmitter-

to receiver.

Receiver-to-transmitter communication is accomplished by modulating the load seen by the receiver's coil; the communication is purely digital

and symbols 1’s and 0’s carried on the power signal. Modulation is done with amplitude-shift keying (ASK) modulation using with a bit-rate of

2Kbps. To the transmitter, this appears as an impedance change, which results in measurable variations of the transmitter’s coil. The power

transmitter demodulates this variation of the coil current or voltage to receive the packets.

Transmitter-to-receiver communication is accomplished by frequency-shift keying (FSK) modulation over the power signal frequency. The

power transmitter P9242-R has the means to modulate FSK data from the power signal frequency and use it in order to establish the

handshaking protocol with the power receiver.

The P9242-R implements FSK communication when used in conjunction with WPC-compliant receivers, such as the P9221-R. The FSK

communication protocol allows the transmitter to send data to the receiver using the power transfer link in the form of modulating the power

frequency.

Communication packets are transmitted from transmitter to receiver with less than 1% positive frequency deviation following any receiver-to-

transmitter communication packet. The frequency deviation is calculated using Equation 1.

60000

60000

[KHz]

Equation 1

the frequency of the internal oscillator responsible for counting the period of the power transfer signal.

The FSK byte-encoding scheme and packet structure complies with the WPC specification revision 1.2.2. The FSK communication uses a

Figure 18. Example of Differential Bi-phase Encoding for FSK

ONE

ZERO

ONE

ZERO

ONE

ONE

ZERO

ZERO

512 cycles

256 cycles

Each byte will comply with the start, data, parity, and stop asynchronous serial format structure shown in Figure 19:

Figure 19. Example of Asynchronous Serial Byte Format for FSK

Start

Stop

Parity

b

0

1

2

3

4

5

6

7

b

b

b

b

b

b

b