P9242-R Datasheet

© 2016 Integrated Device Technology, Inc

3

December 16, 2016

13. Recommended Land Pattern......................................................................................................................................................................29

14. Special Notes: NDG 48-VFQFN Package Assembly..................................................................................................................................30

15. Marking Diagram ........................................................................................................................................................................................30

16. Ordering Information...................................................................................................................................................................................30

17. Revision History..........................................................................................................................................................................................31

List of Figures

Figure 1. Pin Assignments..................................................................................................................................................................................5

Figure 2. Efficiency vs. Output Load: VOUT_RX = 12V.........................................................................................................................................11

Figure 3. Efficiency vs. Output Load: VOUT_RX = 9V...........................................................................................................................................11

Figure 4. Efficiency vs. Output Load: VOUT_RX = 5V...........................................................................................................................................11

Figure 5. Load Regulation vs. Output Load: VCC_5V in schematic Figure 24 .................................................................................................11

Figure 6. Load Regulation vs. Output Load: LDO33.........................................................................................................................................11

Figure 7. Load Regulation vs. Output Load: LDO18.........................................................................................................................................11

Figure 8. Over-Current Limit vs. VILIM ...............................................................................................................................................................12

Figure 9. Voltage and Current Signal for Demodulation ...................................................................................................................................12

Figure 10. Enable Startup...................................................................................................................................................................................12

Figure 11. Communication Packet during RX Load Step from 0 to 1.3A............................................................................................................12

Figure 12. Communication Packet during RX Load Step from 1.3A to 0............................................................................................................12

Figure 13. Functional Block Diagram..................................................................................................................................................................13

Figure 14. Voltage Mode Envelope Detector......................................................................................................................................................14

Figure 15. Current Mode Envelope Detector ......................................................................................................................................................15

Figure 16. NTC Thermistor Connection to TS Pin ..............................................................................................................................................15

Figure 17. UVLO Threshold Definition................................................................................................................................................................17

Figure 18. Example of Differential Bi-phase Encoding for FSK ..........................................................................................................................18

Figure 19. Example of Asynchronous Serial Byte Format for FSK.....................................................................................................................18

Figure 20. Bit Decoding Scheme ........................................................................................................................................................................19

Figure 21. Byte Decoding Scheme .....................................................................................................................................................................19

Figure 22. Communication Packet Structure ......................................................................................................................................................19

Figure 23. WPC Power Transfer Phases Flow Chart .........................................................................................................................................20

Figure 24. P9242-R Typical Application Schematic............................................................................................................................................25

Figure 25. 48-VFQFN Package Outline Drawing................................................................................................................................................28

Figure 26. 48-VFQFN Land Pattern Drawing .....................................................................................................................................................29