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ADA4350ARUZ-R7 数据表(PDF) 17 Page - Analog Devices

部件名 ADA4350ARUZ-R7
功能描述  FET Input Analog Front End with ADC Driver
PDF  38 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADA4350ARUZ-R7 数据表(HTML) 17 Page - Analog Devices

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ADA4350
Data Sheet
Rev. B | Page 16 of 37
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RF1
VOUT1
FB5
FB2
FB3
FB4
SWB_OUT
SWA_OUT
VOUT2
REF
SDI/P3
CS/P4
DVDD
FB1
FB0
IN-N
SWB_IN
–VS
SWA_IN
IN-P
SDO/P2
SCLK/P1
LATCH/P0
EN
+VS
MODE
DGND
VIN1
ADA4350
(Not to Scale)
TOP VIEW
Figure 5. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SWB_OUT
Switch Group B (S3 to S5 and S9 to S11) Output.
2
RF1
Feedback Resistor for Output Differential Amplifier.
3
VOUT1
Differential Amplifier Output 1.
4
FB5
Feedback Pin 5 for FET Input Amplifier.
5
FB4
Feedback Pin 4 for FET Input Amplifier.
6
FB3
Feedback Pin 3 for FET Input Amplifier.
7
FB2
Feedback Pin 2 for FET Input Amplifier.
8
FB1
Feedback Pin 1 for FET Input Amplifier.
9
FB0
Feedback Pin 0 for FET Input Amplifier.
10
IN-N
FET Input Amplifier Inverting Input.
11
IN-P
FET Input Amplifier Noninverting Input.
12
SWA_IN
Switch Group A (S0 to S2 and S6 to S8) Input.
13
SWB_IN
Switch Group B (S3 to S5 and S9 to S11) Input.
14
−VS
Analog Negative Supply.
15
+VS
Analog Positive Supply.
16
EN
Enable Pin.
17
MODE
Mode Pin. Use this pin to switch between the SPI interface and the parallel interface.
18
DGND
Digital Ground.
19
LATCH/P0
Latch Bit in the Serial Mode (LATCH). Parallel Data Bit 0 in parallel mode (P0).
20
SCLK/P1
Digital Clock in Serial Mode (SCLK). Parallel Data Bit 1 in parallel mode (P1).
21
SDO/P2
Serial Data Out in Serial Mode (SDO). Parallel Data Bit 2 in parallel mode (P2).
22
SDI/P3
Serial Data In in Serial Mode (SDI). Parallel Data Bit 3 in parallel mode (P3).
23
CS/P4
Select Bit in Serial Mode (CS). Parallel Data Bit 4 in parallel mode (P4).
24
DVDD
Digital Positive Supply.
25
REF
Reference for the ADC Driver at M1.
26
VOUT2
Differential Amplifier Output 2.
27
SWA_OUT
Switch Group A (S0 to S2 and S6 to S8) Output.
28
VIN1
Differential Amplifier Noninverting Input.



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