ADA4530-1ARZ-R7 datasheet(29/51 Pages) AD

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ADA4530-1

Data Sheet

Rev. A | Page 28 of 50

THEORY OF OPERATION

The ADA4530-1 is an operational amplifier specifically

designed to interface with the extremely high impedance

sensors used in electrometer applications.

A MOSFET input stage eliminates the gate leakage currents

associated with legacy junction gate field effect transistor

(JFET) electrometers. The ADA4530-1 achieves extremely low

input bias currents while simultaneously providing robust

protection against ESD damage. A unique ESD diode structure

provides protection while also allowing the diodes to be

guarded to minimize leakage currents to the input pins. The

ADA4530-1 integrates the precision buffer used to guard

internal ESD diode leakage paths. The output of this guard

buffer is also connected to external pins to allow the user to

guard external components against leakage currents.

The input bias current is determined by the accuracy of the

guard voltage applied across the ESD diodes. The offset voltages

of the amplifier and guard buffer set the accuracy of the guard

voltage and, therefore, the input bias current.

The ADA4530-1 uses Analog Devices, Inc., DigiTrim™

technology to achieve its superior performance.

DigiTrim is used to trim the offset voltage of the amplifier and

guard buffer to reject changes in the common-mode voltage,

power supply voltage, and temperature. This technique

significantly improves VOS, CMRR, PSRR, and TCVOS

specifications.

Figure 99 shows the simplified schematic of the ADA4530-1.

The amplifier uses a three-stage architecture with a fully

differential input stage to achieve excellent dc performance

specifications.

ESD STRUCTURE

The input ESD structure consists of Diode D1 to Diode D6.

The noninverting input is coupled to the guard pins (GRD)

by the D1 and D2 antiparallel diodes. The inverting input is

coupled to the guard pins by the D3 and D4 antiparallel diodes.

The guard pins are connected to the power supplies through

Diode D5 and Diode D6. During ESD events, the transient

current flows from the input pins through one of the antiparallel

diodes and harmlessly into the supplies through one of the power

supply diodes. During normal operation, the guard buffer (BUF1)

forces the voltage across the antiparallel diodes to 0 V. Resistor R1

shields the guard buffer from potentially large capacitances

connected to the guard pins. Its value is nominally 1 kΩ.

INPUT STAGE

The input stage comprises a PMOS differential pair (M1, M2),

folded cascode transistors (M5 to M12), and current source I1.

The ADA4530-1 achieves its high performance specifications by

using low voltage MOS devices for its differential inputs. These

low voltage MOS devices offer better 1/f noise and bandwidth

per unit current compared to high voltage devices. The input

stage is isolated from the high system voltages with proprietary

protection circuitry. This regulation circuitry protects the input

devices from the high supply voltages in which the amplifier

can operate.

The proprietary high voltage protection circuitry in the

ADA4530-1 operates in such a way that it minimizes the

common-mode voltage changes seen by the amplifier input

stage for most of the input common-mode range. This circuitry

results in excellent disturbance rejection when operating in this

preferred input common-mode range. The performance

benefits of operating within this preferred range are shown in

the VOS vs. VCM graphs (see Figure 16 to Figure 18), the small

signal CMRR vs. VCM graph (see Figure 21), and the small signal

PSRR vs. VCM graph (see Figure 54).

These input devices are protected from large differential input

voltages by the antiparallel ESD diodes (D1 to D4). The diodes

can conduct significant current when the differential voltage

exceeds 700 mV. The user must ensure that the current flowing

into the input pins is limited to the absolute maximum of 10 mA.

V–

V+

+IN

–IN

GRD

M11

M12

M10

M15

M16

M14

M13

M21

M19

M20

M18

M17

M22

BUF1

HIGH VOLTAGE PROTECTION

M3 M4

OUT

Figure 99. Simplified Schematic

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