ADE9078ACPZ datasheet(63/108 Pages) AD

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ADE9078

Data Sheet

Rev. 0 | Page 62 of 107

ACCESSING ON-CHIP DATA

SPI PROTOCOL OVERVIEW

The ADE9078 has a SPI-compatible interface, consisting of four

pins: SCLK, MOSI, MISO, and SS. The ADE9078 is always a SPI

slave—it never initiates SPI communication. The SPI interface

is compatible with 16-bit and 32-bit read/write operations. See

the Register Information section for information about the

length of each register.

Figure 96 shows the connection between the ADE9078 SPI and

a master device that contains a SPI interface.

ADE9078

SPI MASTER

MOSI

MISO

SCLK

MOSI

MISO

SCK

Figure 96. Connecting the ADE9078 Slave SPI Port to a Master SPI Device

The SS pin is the chip select input. It starts the SPI

communication with the ADE9078.

There are three parts to the ADE9078 SPI protocol: first a 16-bit

command is sent, which indicates whether to perform a read or

write operation and which register to access. This is followed by

the 16- or 32-bit data to write, in the case of a SPI write, or the

data read from the register, in the case of a SPI read operation.

Finally, in the case of a SPI read operation, a cyclic redundancy

check (CRC) of the register data follows, unless the address is in a

region that supports burst reading, in which case the data from

the next register follows (see the SPI Burst Read section for

more information).

The SS input must stay low for the whole SPI transaction. Bringing

SS high during a data transfer operation aborts the transfer. A

new transfer can be initiated by returning the SS logic input low.

It is not recommended to tie SS to ground because the high to

low transition on SS starts the ADE9078 SPI transaction.

Data shifts into the device at the MOSI logic input on the falling

edge of SCLK, and the device samples the input data on the rising

edge of SCLK. Data shifts out of the ADE9078 at the MISO logic

output on the falling edge of SCLK and must be sampled by the

master device on the rising edge of SCLK. The MSB of the word

is shifted in and out first.

MISO has an internal weak pull-up of 100 kΩ, making the default

state of the MISO pin high. It is possible to share the SPI bus with

multiple devices, including multiple ADE9078 devices, if desired.

The ADE9078 is compatible with the following microcontroller

SPI port clock polarity and phase settings: CPOL = 0 and

CPHA = 0 (typically Mode 0) or CPOL = 1 and CPHA = 1

(typically Mode 3).

Note that the default state of the MOSI pin depends on the

master SPI device. In Figure 97, Figure 98, and Figure 100, it is

assumed to be high (Logic 1).

SCLK

MOSI

CMD_HDR = 0x6078

MISO

AIRMS AT 0x607 32 BITS

AIRMS AT 0x607 32 BITS BIRMS AT 0x608 32 BITS

CRC, 16 BITS

0 15

MISO

BURST_EN = 0

ADDRESS 0x500 TO

ADDRESS 0x6FF

BURST_EN = 1,

ADDRESS 0x500 TO

ADDRESS 0x6FF

Figure 97. SPI Read Protocol Example—CRC or Next Data Can Follow

SCLK

MOSI

MISO

CMD_HDR = 0x00B0

AVGAIN AT 0x00B

Figure 98. SPI Write Protocol Example

The maximum serial clock frequency supported by this

interface is 10 MHz.

The SPI read/write operation starts with a 16-bit command

(CMD_HDR), which contains the following information:



CMD_HDR, Bits[15:4] are the 12 MSBs of the command

header, and contains the address of the register (ADDR,

Bits[11:0]) to be read or written.



CMD_HDR, Bit 3 is the bit that specifies if the current

operation is read/write. Set this bit to 1 for read and 0 for

write.



CMD_HDR, Bits[2:0] are required for internal chip timing

and can be 1s or 0s. Note that these bits are read back as

000 in the LAST_CMD register.

Figure 99 shows the information contained in the command

header.

ADDR[11:0]

R/W

xxx

READ = 1

WRITE = 0

DON’T CARE BITS

ADDRESS TO BE ACCESSED

Figure 99. Command Header, CMD_HDR, Bits[15:0]

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