ADE9078ACPZ datasheet(64/108 Pages) AD

64 / 108 page

Data Sheet

ADE9078

Rev. 0 | Page 63 of 107

SPI WRITE

A write operation using the SPI interface of the ADE9078 is initiated

when the SS pin goes low and the ADE9078 receives a 16-bit

command header (CMD_HDR), with CMD_HDR, Bit 3 = 0.

The 16-bit or 32-bit data to write follows the command header,

with the MSB first.

After the last bit of data has been clocked out, the master brings

the SS line high to release the SPI bus. It is recommended to

have the SCLK line idle high.

SPI READ

A read operation using the SPI interface of the ADE9078 is initiated

when the SS pin goes low and the ADE9078 receives a 16-bit com-

mand header (CMD_HDR), with CMD_HDR, Bit 3 = 1.

The 16-bit or 32-bit data from the register follows the command

header, with the MSB first.

The CRC of the register data is appended if

•

BURST_EN = 0 and the address is within the range of

Address 0x000 to Address 0x6FF.

•

BURST_EN = 0 and the address is in the waveform buffer,

Address 0x800 to Address 0xFFF and BURST_CHAN = 1111b.

The ADE9078 provides a SPI burst read functionality—instead

of sending the CRC, the following data is sent from the next

address if these conditions apply (see the SPI Burst Read section

for more information):

•

BURST_EN = 1 and the address is within the range of

Address 0x500 to Address 0x516, Address 0x600 to

Address 0x63C, or Address 0x680 to Address 0x6BC.

•

The address is within the range of Address 0x800 to

Address 0xFFF and BURST_CHAN is not equal to 1111b.

If none of these cases apply, and extra clocks are sent, the

original read data is resent.

Table 25 summarizes what data is sent after the data from the

address being accessed and the BURST_EN selection.

Table 25. Data Clocked Out After Addressed Data in SPI

Read Operation

Address

BURST_EN = 0

BURST_EN = 1

0x000 to 0x4FF

CRC

Same data is resent

0x500 to 0x6FF

CRC

Next address

0x800 to 0xFFF

(Waveform Buffer)

If BURST_CHAN =

1111, CRC;

otherwise, next

address

If BURST_CHAN =

1111, the same data

is resent; otherwise,

next address

If this information is not needed in the application, the SS line

can be brought high before clocking out the CRC.

After the last bit of data, or CRC, is clocked out, the master

must bring the SS line high to release the SPI bus. Then the

ADE9078 stops driving MISO and enables a 100 kΩ weak pull-

up. It is recommended to have the SCLK line idle high.

An example of what happens when reading the AVGAIN register,

Address 0x00B, when BURST_EN = 0 and 1, is given in Figure 100.

SCLK

MOSI

CMD_HDR = 0x00B8

MISO

AVGAIN AT 0x00B

CRC, 16 BITS

0 15

MISO

BURST_EN = 0

ADDRESS 0x000 TO

ADDRESS 0x6FF

BURST_EN = 1,

ADDRESS 0x000 TO

ADDRESS 0x6FF

AVGAIN AT 0x00B AVGAIN AT 0x00B

Figure 100. SPI Read Protocol Example Where the Following Data Is the CRC

or the Initial Data Is Repeated

SPI BURST READ

SPI burst read allows multiple registers to be read after sending

one CMD_HDR. After the register data has been clocked out,

the ADE9078 auto-increments the address and starts clocking

out the data from the next register address.

SPI burst read access is available on registers with addresses

ranging from Address 0x500 to Address 0x6FF and in the

waveform buffer, with Address 0x800 to Address 0xFFF. SPI

burst read is not available on other register addresses. A SPI

burst read operation occurs for the options in Table 25 where

the next address is written.

To enable burst read functionality on the registers from

Address 0x500 to Address 0x6FF, set the BURST_EN bit in

the CONFIG1 register to 1.

The waveform buffer burst read functionality is enabled by default

and is managed by BURST_CHAN in the WFB_CFG register. If

these bits are set to 1111b, the burst read functionality of the

waveform buffer is disabled. For further details on the burst

read operation of waveform buffer contents, see the Burst Read

Waveform Buffer Samples from SPI section.

A burst read operation using the SPI interface of the ADE9078

is initiated when the SS pin goes low and the ADE9078 receives a

16-bit command header (CMD_HDR), with CMD_HDR, Bit 3 = 1

that meets the criteria in Table 25 where the next address is written.

Following the command header, the ADE9078 sends the register

data for the register addressed in the command. After the last bit

of the first register value is received, the ADE9078 auto-increments

the address and starts clocking out the data from the next register

address. This process continues until the master sets the SS line

high. If the starting address is in the range of Address 0x500 to

Address 0x516 and the SPI is clocked beyond Address 0x516,

the address is auto-incremented until it reaches Address 0x5FF

and then wraps back to the initial address. If the initial address

is in the Address 0x600 to Address 0x63C or Address 0x680 to

Address 0x6BC range and the SPI is clocked beyond Address 0x63C

or Address 0x6BC, it wraps back to the initial address. Note that

certain reserved registers in the valid SPI burst address range

reads zero during burst read operation.

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