ADE9078ACPZ datasheet(12/108 Pages) AD

12 / 108 page

Data Sheet

ADE9078

Rev. 0 | Page 11 of 107

Pin No.

Mnemonic

Description

19, 20

VAN, VAP

Analog Inputs, Channel VA. The VAP (positive) and VAN (negative) inputs are fully differential voltage

inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

21, 22

VBN, VBP

Analog Inputs, Channel VB. The VBP (positive) and VBN (negative) inputs are fully differential voltage

inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

23, 24

VCN, VCP

Analog Inputs, Channel VC. The VCP (positive) and VCN (negative) inputs are fully differential voltage

inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.

AVDDOUT

1.9 V Output of the Analog Low Dropout Regulator (LDO). Decouple AVDDOUT with a 0.1 µF ceramic

capacitor in parallel with a ceramic 4.7 µF capacitor. Do not connect external active circuitry to this pin.

AGND

Analog Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.

VDD

Supply Voltage. The VDD pin provides the supply voltage. Decouple VDD to GND with a ceramic 0.1 µF

capacitor in parallel with a ceramic 10 µF capacitor.

GND

Supply Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.

CLKIN

Crystal/Clock Input. Connect a crystal across CLKIN and CLKOUT to provide a clock source. See the Crystal

Selection section for details on choosing a suitable crystal. Alternatively, an external clock can be

provided at this logic input.

CLKOUT

Crystal Output. Connect a crystal across CLKIN and CLKOUT to provide a clock source. When using CLKOUT

to drive external circuits, connect an external buffer. When using an external clock on CLKIN, leave

CLKOUT unconnected.

IRQ0

Interrupt Request Output. This pin is an active low logic output. See the Interrupts/Events section for

information about events that trigger interrupts.

IRQ1

Interrupt Request Output. This pin is an active low logic output. See the Interrupts/Events section for

information about events that trigger interrupts.

CF1

Calibration Frequency (CF) Logic Output 1. The CF1, CF2, CF3, and CF4 outputs provide power

information based on the CFxSEL bits in the CFMODE register. Use these outputs for operational and

calibration purposes. Scale the full-scale output frequency by writing to the CFxDEN registers (see the

Digital to Frequency Conversion—CFx Output section).

CF2

CF Logic Output 2. This pin indicates CF2.

CF3/ZX

CF Logic Output 3/Zero Crossing. This pin indicates CF3 or zero crossing.

CF4/EVENT/DREADY

CF Logic Output 4/Event Pin/Data Ready. This pin indicates CF4, events, or when new data is ready.

SCLK

Serial Clock Input for the SPI Port. All serial data transfers synchronize to this clock (see the Accessing

On-Chip Data section). The SCLK pin has a Schmitt trigger input for use with a clock source that has a

slow edge transition time, for example, optoisolator outputs.

MISO

Data Output for the SPI Port.

MOSI

Data Input for the SPI Port.

Slave Select for the SPI Port.

Exposed Pad. Create a similar pad on the printed circuit board (PCB) under the exposed pad. Solder the

exposed pad to the pad on the PCB to confer mechanical strength to the package and connect all

grounds (GND, AGND, DGND, and REFGND) together at this point.

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