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Data Sheet

ADP2443

Rev. 0 | Page 13 of 24

THEORY OF OPERATION

The ADP2443 is synchronous step-down, dc-to-dc regulator that

uses an emulated current-mode architecture with an integrated

high-side power switch and a low-side synchronous rectifier.

The regulator targets high performance applications that require

high efficiency and design flexibility.

The ADP2443 operates with an input voltage from 4.5 V to 36 V

and regulates the output voltage down to 0.6 V. Additional features

that maximize design flexibility include programmable switching

frequency, programmable soft start, external compensation,

precision enable, and a power-good output.

CONTROL SCHEME

The ADP2443 uses a fixed frequency, current mode PWM control

architecture to achieve high efficiency and low noise operation.

The ADP2443 operates at a fixed frequency set by an external

resistor from RT/SYNC to GND. It uses the low side NFET current

for the PWM control as shown in Figure 32. The valley current

information is captured at the end of the off period and combines

with the slope ramp to form the emulated current ramp voltage.

The slope ramp voltage is controlled by the resistor between

RAMP and PVIN. At the start of each oscillator cycle, the high-

side NFET turns on and the inductor current increases until the

emulated current ramp voltage crosses the COMP voltage, which

turns off the high-side NFET and turns on the low-side NFET,

which in turn places a negative voltage across the inductor,

causing a reduction in the inductor current. The low-side NFET

stays on for the remainder of the cycle.

PWM

CLK

VRAMP

IRAMP

PVIN

VOUT

VCOMP

COUT

RTOP

RBOT

0.6V

– ACS

Figure 32. PWM Control Scheme

PRECISION ENABLE/SHUTDOWN

The EN input pin has a precision analog threshold of 1.2 V

(typical) with 100 mV of hysteresis. When the enable voltage

exceeds 1.2 V, the regulator turns on; when it falls below 1.1 V

(typical), the regulator turns off. To force the regulator to start

automatically when input power is applied, connect EN to PVIN.

The precision EN pin has an internal pull-down current source

(0.13 µA) that provides a default turn-off when the EN pin is open.

When the EN pin voltage exceeds 1.2 V (typical), the ADP2443

is enabled and the internal pull-up current increases to 4 µA, which

allows users to program the PVIN UVLO and hysteresis.

INTERNAL REGULATOR (VREG)

The on-board 5 V regulator provides a stable supply for the

internal circuits. It is recommended that a 1 µF ceramic capacitor

be placed between the VREG pin and GND. The internal regulator

includes a current-limit circuit to protect the output if the

maximum external load current is exceeded.

BOOTSTRAP CIRCUITRY

The ADP2443 includes a regulator to provide the gate drive

voltage for the high-side N-MOSFET. It uses differential sensing

to generate a 5 V bootstrap voltage between the BST and SW pins.

It is recommended that a 0.1 µF, X7R or X5R ceramic capacitor

be placed between the BST pin and the SW pin.

OSCILLATOR

The switching frequency of ADP2443 is controlled by the

RT/SYNC pin. A resistor from RT/SYNC to GND programs the

switching frequency according to the following equation:

)

kΩ

(

000

168

(kHz)

A 280 kΩ resistor sets the frequency to 600 kHz, and a 560 kΩ

resistor sets the frequency to 300 kHz. Figure 33 shows the

typical relationship between fSW and RT.

2200

800

1400

2000

600

1200

1800

400

200

1000

1600

100

200

300

400

500

700

600

800

900

RT (kΩ)

Figure 33. Switching Frequency vs. RT

SYNCHRONIZATION

To synchronize the ADP2443, connect an external clock to the

RT/SYNC pin. The frequency of the external clock can be in the

range of 200 kHz to 1.8 MHz. During synchronization, the reg-

ulator operates in continuous conduction mode (CCM) and the

rising edge of the switching waveform runs 180° out of phase to

the rising edge of the external clock.

When the ADP2443 is operating in synchronization mode,

a resistor must be connected from the RT/SYNC pin to GND

to program the internal oscillator to run at 80% to 120% of the

external synchronization clock.

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