ADP2443

Data Sheet

Rev. 0 | Page 14 of 24

SOFT START

The ADP2443 uses the SS pin to program the soft start time.

Place a capacitor between SS and GND; an internal current

charges this capacitor to establish the soft start ramp. Calculate

SS

SS

SS

I

C

t

×

=

V

6

.

0

where:

If the output voltage is precharged before power up, the ADP2443

prevents the low-side MOSFET from turning on until the soft

start voltage exceeds the voltage on the FB pin.

POWER GOOD

The power-good pin (PGOOD) is an active high, open-drain

output that requires an external resistor to pull it up to a

voltage. A logic high on the PGOOD pin indicates that the

voltage on the FB pin (and therefore the output voltage) is

within regulation.

The power-good circuitry monitors the output voltage on the

FB pin and compares it to the rising and falling thresholds that

are specified in Table 1. If the rising output voltage exceeds the

target value, the PGOOD pin is held low. The PGOOD pin

continues to be held low until the falling output voltage returns

to the target value.

If the output voltage falls below the target output voltage, the

PGOOD pin is held low. The PGOOD pin continues to be held

low until the rising output voltage returns to the target value.

The power-good rising and falling thresholds are shown in

Figure 34. There is always a 16-cycle waiting period (deglitch)

before the PGOOD pin is pulled from low to high or from high

to low.

16-CYCLE

DEGLITCH

16-CYCLE

DEGLITCH

16-CYCLE

DEGLITCH

16-CYCLE

DEGLITCH

110%

105%

100%

95%

90%

PGOOD

Figure 34. PGOOD Rising and Falling Thresholds

PEAK CURRENT-LIMIT AND SHORT-CIRCUIT

PROTECTION

The ADP2443 uses the emulated current ramp voltage for cycle-

by-cycle current limit protection to prevent current runaway. When

the emulated current ramp voltage reaches the valley current

limit threshold plus the ramp voltage, the high-side MOSFET

turns off and the low-side MOSFET turns on until the next cycle.

The overcurrent counter increments during this process; otherwise

the overcurrent counter decreases. If the overcurrent counter reaches

10 or the FB voltage drops below 0.2 V after the soft start, the

device enters hiccup mode. During hiccup mode, the high-side

NFET and low-side NFET are both turned off. The device remains

in this mode for seven soft start cycles and then attempts to restart

with soft start. If the current-limit fault is cleared, the device

resumes normal operation; otherwise, it reenters hiccup mode.

PWM

SW

CURRENT-LIMIT

COMPARATOR

PVIN

HICCUP

CONTROL

BLOCK

CYCLE-BY-CYCLE

THRESHOLD

Figure 35. Current-Limit Circuit

PWM

CYCLE-BY-CYCLE PEAK

CURRENT-LIMIT THRESHOLD

VALLEY

CURRENT-LIMIT

THRESHOLD

Figure 36. Cycle-By-Cycle Current-Limit Waveform

OVERVOLTAGE PROTECTION (OVP)

The ADP2443 includes an OVP feature to protect the regulator

against an output short to a higher voltage supply or when a strong

load disconnect transient occurs. If the feedback voltage increases

to 0.7 V, the internal high-side MOSFET and low-side MOSFET

are turned off until the voltage at the FB pin decreases to 0.63 V.

At that time, the ADP2443 resumes normal operation.

UNDERVOLTAGE LOCKOUT (UVLO)

UVLO circuitry is integrated in the ADP2443 to prevent the

3.9 V typical, the device shuts down and both the power switch

again above 4.3 V typical, the soft start period is initiated and

the device is enabled.

THERMAL SHUTDOWN

If the ADP2443 junction temperature rises above 150°C, the

internal thermal shutdown circuit turns off the regulator for self

protection. Extreme junction temperatures can be the result of high

current operation, poor PCB layout thermal design, and/or high

ambient temperature. A 25°C hysteresis is included in the thermal

shutdown circuit so that, if an overtemperature event occurs, the

ADP2443 does not return to normal operation until the on-chip

temperature drops below 125°C. Upon recovery, a soft start is

initiated before normal operation begins.