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ADP2443ACPZN-R7 数据表(PDF) 18 Page - Analog Devices

部件名 ADP2443ACPZN-R7
功能描述  Process control and industrial automation
PDF  25 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP2443ACPZN-R7 数据表(HTML) 18 Page - Analog Devices

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Data Sheet
ADP2443
Rev. 0 | Page 17 of 24
OUTPUT CAPACITOR SELECTION
The output capacitor selection affects the output ripple voltage
load step transient and the loop stability of the regulator.
For example, during a load step transient where the load is
suddenly increased, the output capacitor supplies the load until
the control loop can ramp up the inductor current. The delay
caused by the control loop causes the output to undershoot.
Calculate the output capacitance that is required to satisfy the
voltage droop requirement using the following equation:
COUT_UV =
UV
OUT
OUT
IN
STEP
UV
V
V
V
L
I
K
_
2
)
(
2
∆
×
−
×
×
∆
×
where:
KUV is a factor, with a typical setting of KUV = 2.
ΔISTEP is the load step.
ΔVOUT_UV is the allowable undershoot on the output voltage.
Another example occurs when a load is suddenly removed from
the output, and the energy stored in the inductor rushes into
the output capacitor, causing the output to overshoot.
Calculate the output capacitance that is required to meet the
overshoot requirement using the following equation:
COUT_OV =
2
2
_
2
)
(
OUT
OV
OUT
OUT
STEP
OV
V
V
V
L
I
K
−
∆
+
×
∆
×
where:
KOV is a factor, with a typical setting of KOV = 2.
ΔVOUT_OV is the allowable overshoot on the output voltage.
The output ripple is determined by the effective series resistance
(ESR) and the value of the capacitance. Use the following equation
to select a capacitor that can meet the output ripple requirements:
COUT_RIPPLE =
RIPPLE
OUT
SW
L
V
f
I
_
8
∆
×
×
∆
where ΔVOUT_RIPPLE is the allowable output ripple voltage.
RESR =
L
RIPPLE
OUT
I
V
∆
∆
_
where RESR is the equivalent series resistance of the output
capacitor in ohms (Ω).
Select the largest output capacitance given by COUT_UV, COUT_OV,
and COUT_RIPPLE to meet both load transient and output ripple
performance.
The selected output capacitor voltage rating must be greater
than the output voltage. The rms current rating of the output
capacitor must be greater than the value that is calculated by
using the following equation:
ICOUT_RMS =
12
L
I
∆
PROGRAMMING INPUT VOLTAGE UVLO
The ADP2443 has a precision enable input to program the
UVLO threshold of the input voltage (see Figure 37).
4µA
0.13µA
ADP2443
1.2V
EN CMP
PVIN
EN
RTOP_EN
RBOT_EN
Figure 37. Programming the Input Voltage UVLO
Use the following equation to calculate RTOP_EN and RBOT_EN:
µA
3.87
V
1.2
µA
0.13
V
1.1
V
2
.
1
V
1
.
1
_
_
_
×
+
×
×
−
×
=
FALLING
IN
RISING
IN
EN
TOP
V
V
R
where:
VIN_RISING is the VIN rising threshold.
VIN_FALLING is the VIN falling threshold.
V
1.2
µA
0.13
V
2
.
1
_
_
_
_
−
×
−
×
=
EN
TOP
RISING
IN
EN
TOP
EN
BOT
R
V
R
R
SLOPE COMPENSATION SETTING
The slope compensation is necessary in a current mode control
architecture to prevent subharmonic oscillation and to maintain a
stable output. The ADP2443 uses the emulated current mode
and the slope compensation is implemented by connecting a
resistor (RRAMP) between the RAMP pin and PVIN pin.
Theoretically, an extra slope of VOUT/(2 × L) is enough to
stabilize the system. To guarantee that any noise is decimated in
one cycle and the system is stable from subharmonic oscillation,
the ADP2443 uses an extra slope of VOUT/L.
Calculate the ramp resistor value, RRAMP, using the following
equation:
12
10
3.9
RAMP
L
R
×
=
where L is the inductor value.
COMPENSATION DESIGN
The ADP2443 uses an emulated current mode control
architecture that combines the fast line transient response of
traditional peak current mode with the capability to convert a
high input voltage to a very low output voltage. Furthermore,
the small signal characteristics of the emulated current mode
are almost identical to those of traditional peak current mode.
Therefore, the compensation network design method used in
traditional peak current mode can also be applied to the
emulated current mode control.
The power stage can be simplified as a voltage controlled current
source supplying current to the output capacitor and load resistor.
It is composed of one domain pole and a zero.



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