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ADP7182ACPZ-R7 数据表(PDF) 29 Page - Analog Devices

部件名 ADP7182ACPZ-R7
功能描述  Positive or negative enable logic
PDF  31 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP7182ACPZ-R7 数据表(HTML) 29 Page - Analog Devices

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Data Sheet
ADP7182
Rev. I | Page 29 of 31
Table 11. Recommended LDOs for Very Low Noise Operation
Device
Number
VIN
Range (V)
VOUT
Fixed (V)
VOUT
Adjust
(V)
IOUT
(mA)
IQ at
IOUT
(µA)
IGND-SD
Max
(µA)
Soft
Start
PGOOD
Noise
(Fixed)
10 Hz to
100 kHz
(µV rms)
PSRR
100 kHz
(dB)
PSRR
1 MHz
(dB)
Package
ADP7102
3.3 to 20
1.5 to 9
1.22 to
19
300
750
75
No
Yes
15
60
40
3 mm × 3 mm
8-lead LFCSP,
8-lead SOIC
ADP7104
3.3 to 20
1.5 to 9
1.22 to
19
500
900
75
No
Yes
15
60
40
3 mm × 3 mm
8-lead LFCSP,
8-lead SOIC
ADP7105
3.3 to 20
1.8, 3.3, 5
1.22 to
19
500
900
75
Yes
Yes
15
60
40
3 mm × 3 mm
8-lead LFCSP,
8-lead SOIC
ADP7118
2.7 to 20
1.2 to 5
1.2 to 19
200
160
10
Yes
No
11
68
50
2 mm × 2 mm
6-lead LFCSP,
8-lead SOIC,
5-lead TSOT
ADP7142
2.7 to 40
1.2 to 5
1.2 to 39
200
160
10
Yes
No
11
68
50
2 mm × 2 mm
6-lead LFCSP,
8-lead SOIC,
5-lead TSOT
ADP7182
−2.7 to
−28
−1.8 to
−5
−1.22 to
−27
−200
−650
−8
No
No
18
45
45
2 mm × 2 mm
6-lead LFCSP,
3 mm × 3 mm
8-lead LFCSP,
5-lead TSOT



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