LM79 datasheet(3/31 Pages) NSC

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Block Diagram

Pin Description

Name(s)

Number

of Pins

Type

Description

IORD

Digital Input

An active low standard ISA bus I/O Read Control.

IOWR

Digital Input

An active low standard ISA bus I/O Write Control.

SYSCLK

Digital Input

The reference clock for the ISA bus. Typically ranges from 4.167 MHz to

8.33 MHz. The minimum clock frequency this input can handle is 1 Hz.

D7–D0

4–11

Digital I/O

Bi-directional ISA bus Data lines. D0 corresponds to the low order bit,

with D7 the high order bit.

CC (+5V)

POWER

+5V V

CC power. Bypass with the parallel combination of 10 µF

(electolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors.

GNDD

GROUND

Internally connected to all digital circuitry.

SMI__IN

Digital Input

Chainable SMI (System Management Interrupt) Input. This is an active

low input that propagates the SMI signal to the SMI output of the LM79

via SMI Mask Register Bit 6 and SMI enable Bit 1 of the Configuration

Chassis

Intrusion

Digital I/O

An active high input from an external circuit which latches a Chassis

Intrusion event. This line can go high without any clamping action

regardless of the powered state of the LM79. The LM79 provides an

internal open drain on this line, controlled by Bit 7 of NMI Mask Register

2, to provide a minimum 20 ms reset of this line.

DS100036-3

LM79 数据表(PDF) 3 Page - National Semiconductor (TI)

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