LM79 datasheet(4/31 Pages) NSC

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Pin Description (Continued)

Name(s)

Number

of Pins

Type

Description

Power

Switch

Bypass

Digital Output

An active low open drain output intended to drive an external P-channel

power MOSFET for software power control.

FAN3–FAN1

17–19

Digital Input

0V to +5V amplitude fan tachometer input.

SCL

Digital Input

Serial Bus Clock.

SDA

Digital I/O

Serial Bus bidirectional Data.

RESET

Digital Output

Master Reset, 5 mA driver (open drain), active low output with a 20 ms

minimum pulse width. Available when enabeld via Bit 7 in SMI Mask

VID4/NTEST

Digital

Input/Test

Output

By default an input for the VID4 power supply readout for the system

processor (Pentium/PRO). Can be programmed as a NAND Tree

totem-pole output that provides board-level connectivity testing. Refer to

Section 11.0 on NAND Tree testing.

GNDA

GROUND

Internally connected to all analog circuitry. The ground reference for all

analog inputs.

−IN6

Analog Input

Ground-referred inverting op amp input. Refer to

Section 4.0, “ANALOG

INPUTS”.

FB6

Analog Output

Output of inverting op amp for Input 6. Refer to

Section 4.0, “ANALOG

INPUTS”.

FB5

Analog Output

Output of inverting op amp for Input 5. Refer to

Section 4.0, “ANALOG

INPUTS”.

−IN5

Analog Input

Ground-referred inverting op amp input. Refer to

Section 4.0, “ANALOG

INPUTS”.

IN4–IN0

29–33

Analog Input

0V to 4.096V FSR Analog Inputs.

VID3–VID0

34–37

Digital Input

Inputs for the power supply readouts for system microprocessor

(Pentium/PRO). This value is read in the VID/Fan Divisor Register.

BTI

Digital Input

Board Temperature Interrupt driven by O.S. outputs of additional

temperature sensors such as LM75. Provides internal pull-up of 10 k

Ω.

NMI/IRQ

Digital Output

Non-Maskable Interrupt (open source)/Interrupt Request (open drain).

The mode is selected with Bit 5 of the Configuration Register and the

output is enabled when Bit 2 of the Configuration Register is set to 1.

The default state is disabled and IRQ mode.

SMI

Digital Output

System Management Interrupt (open drain). This output is enabled when

Bit 1 in the Configuration Register is set to 1. The default state is

disabled.

A2–A0

41–43

Digital Input

The three lowest order bits of the 16-bit ISA Address Bus. A0

corresponds to the lowest order bit.

Digital Input

Chip Select input from an external decoder which decodes high order

address bits on the ISA Address Bus. This is an active low input.

TOTAL PINS

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